Xilinx

About: Xilinx is a company organization based out in San Jose, California, United States. It is known for research contribution in the topics: Programmable logic device & Integrated circuit. The organization has 2814 authors who have published 5275 publications receiving 91373 citations. The organization is also known as: Xilinx, Inc. & Xilinx (United States).

Integrated circuit and method of asynchronously routing data in an integrated circuit

Abstract: An integrated circuit enabling asynchronous data communication is disclosed. The integrated circuit comprises a plurality of circuit blocks, each circuit block of the plurality of circuit blocks comprising programmable resources; and a routing network coupled to each circuit block of the plurality of circuit blocks, the routing network enabling asynchronous data communication with the plurality of circuit blocks. Each circuit block of the plurality of circuit blocks synchronously processes data received from the routing network. A method of routing data in an integrated circuit is also disclosed.

Clock doubler circuit and method

Abstract: A clock doubler circuit and method that accept an input clock signal and provide therefrom an output clock signal having twice the frequency of the input clock signal One circuit according to the invention includes an input clock terminal supplying a input clock signal, and a delay line driven by the input clock signal and supplying a plurality of intermediate clock signals delayed from the input clock signal by incremental unit delays A clock multiplexer selects from among these intermediate clock signals, under control of a multiplexer control circuit, the clock signal that is most nearly 90 degrees offset from the input clock signal The selected clock signal is then combined with the input clock signal in an output clock generator to generate an output clock signal having twice the frequency of the input clock signal In one embodiment, the clock doubler circuit includes a delay stage comprising a delay element that can selectively add a half-unit delay to the input clock signal

Multi-boot configuration of programmable devices

Abstract: A programmable device having a multi-boot capability is described. The programmable device may initially load first configuration data for configuring programmable resources of the device. Thereafter, a multi-boot operation may be triggered, causing the device to reconfigure and load second configuration data. Prior to loading the second configuration data, the device may store status information. In some cases, further multi-boot operations may be triggered for loading other configuration data.

Method and apparatus for clock signal performance measurement

Abstract: Method and apparatus for providing a measure of jitter and skew of a clock signal is described. The clock signal may be used as an input to a digital circuit. In one embodiment, a digital delay circuit is used in conjunction with a processing circuit to continuously measure the jitter of an input clock signal, thus providing clock signal performance measurement over time. In another embodiment, a pair of digital delay circuits are used to continuously measure the skew or delay between a reference clock signal and a input clock signal, thus providing a measurement of the skew of the input clock signal over time. The digital delay circuit(s) are formed on-chip, and thus an on-chip determination of jitter or skew may be provided.

Generic Software Framework for Adaptive Applications on FPGAs

Abstract: Adaptive systems are set to become more mainstream, as numerous practical applications in the communications domain emerge. FPGAs offer an ideal implementation platform, combining high performance with flexibility. While significant research has been undertaken in the area of FPGA partial reconfiguration, it has focussed primarily on low-level architecture-specific implementations. Building upon this previous work, we present a system model and software architecture for implementing runtime adaptive applications on FPGAs, separating the control and processing planes and abstracting away the details of hardware reconfiguration from the system designer. Hardware processing components appear as software components in the runtime system, enabling their inclusion in adaptive applications. We present an adaptive wireless application, demonstrating the use of the model and software architecture.