Zoran Corporation

About: Zoran Corporation is a based out in . It is known for research contribution in the topics: Signal & Pixel. The organization has 241 authors who have published 205 publications receiving 4901 citations.

Techniques of motion estimation when acquiring an image of a scene that may be illuminated with a time varying luminance

Abstract: In a digital camera or other image acquisition device, motion vectors between successive image frames of an object scene are calculated from normalized values of pixel luminance in order to reduce or eliminate any effects on the motion calculation that might occur when the object scene is illuminated from a time varying source such as a fluorescent lamp. Calculated motion vectors are checked for accuracy by a robustness matrix.

Ghost signal cancellation system using feedforward and feedback filters for television signals

Abstract: Disclosed is a television ghost cancellation system based on digital filtering. A baseband video signal at the output of the demodulator is lowpass filtered before being digitized at an analog-to-digital converter. The signal is then processed in digital filters to remove the ghosts. The clean digital signal is then passed to a digital-to-analog converter and lowpass filter to become a clean baseband video signal. The digital filters consist of a feedforward section and a feedback section. The coefficients of the digital filters are calculated by digital signal processor, which processes the data stored in First-In-First-Out buffers (FIFOs). The FIFOs are used as outputs, while one FIFO is used as input to the feedback section. The FIFO stores the standard ghost canceler reference (GCR) signal. Switches are controlled by a synchronization separation circuitry. The coefficients of the feedforward section are estimated by processing data stored in the FIFO. The coefficients of the feedback filter are estimated by adapting a virtual finite impulse response (FIR) filter, which processes data stored in the FIFOs. A scheme is provided to optimize the adaptation process. The advantages of this system are stability and efficiency of the feedback section, fast cancellation and small residuals after convergence.

Method and apparatus for an integrated high definition television controller

Abstract: A method and an apparatus for an integrated high definition television controller are described. The integrated high definition digital television controller includes two or more the following functions in a single chip: MPEG2 Transport, Audio and Video Decoders, Video input capture and converter, flexible video scan rate converter, de-interlace processor, display controller and video D/A converters, graphics controller, a unified local bus, N-plane alpha blending, a warping engine, audio digital signal processor, disk drive interface, peripheral bus interfaces, such as PCI bus and local bus interfaces, various I/O peripherals, a bus bridge with a partitioned chip, and a CPU with caches. The integrated controller, in one embodiment, is designed to handle multiple television standards (for example ATSC, ARIB, DVB, AES, SMPTE, ITU) and designed to be deployed in various countries in the world.

Integrated encryption/decryption functionality in a digital TV/PVR system-on-chip

Abstract: A system-on-a-chip (SoC) to process digital audio-video content includes one or more input/output (I/O) interfaces to transmit the digital audio-video content to corresponding I/O devices coupled to the SoC and to receive the digital audio-video content from the corresponding I/O devices. The SoC also includes a cryptographic engine to encrypt the digital audio-video content being transmitted via the I/O interfaces to the corresponding I/O devices and to decrypt the digital audio-video content received via the I/O interfaces from the corresponding I/O devices.

Flexible and scalable architecture for transport processing

Abstract: A transport processor that can be used in a digital audio-video receiver system comprises a front end and a memory interface. The front end receives concurrently a plurality of transport streams, where two or more of the plurality of transport streams can have different formats, and each transport stream includes a plurality of packets. The front end includes a packet processor to create an aggregate transport stream in a single format from the plurality of transport streams. The memory interface is an interface through which the transport processor can store the aggregate transport stream in a memory for use by subsequent decode and display operations.