Zoran Corporation

About: Zoran Corporation is a based out in . It is known for research contribution in the topics: Signal & Pixel. The organization has 241 authors who have published 205 publications receiving 4901 citations.

Digital video recorder wide dynamic range optical power calibration

Abstract: A method and apparatus are presented for optimizing write operations for optical storage media. A determination is made, at least in part by iteration, of a next power range and a current score for a current power range. If it is determined that the current score is relatively equivalent to a maximum score, a plurality of final parameters is updated and provided, including an optimal power range and a final score. If it is determined that the current score is relatively greater than the final score, then the plurality of final parameters is updated. If it is determined that a maximum number of iterations has been performed, the plurality of final parameters is provided. Otherwise, the current power range is updated with the next power range. One or more of the returned plurality of final parameters are employed to optimize write operations for optical storage media. Determination of the score may also include determining validity of test data segments, selecting a score calculation criterion, and calculating the score based at least in part on the score calculation criterion and on a number and a sequence of valid test data segments. The score calculation criterion may be based on such criterion as beta criterion or modulation amplitude.

Method and apparatus for utilizing device access idle time for input sensing

Abstract: A circuit capable of reading an input from a device on one pin of an integrated circuit package during one time period and either writing data to another device or reading an input from the other device through the same pin during another time period. In one exemplary implementation in which the one pin is used to write data to the other device, the circuit may sense when data is not being written and change the function of the one pin from that of an output pin to that of an input pin until such time as further data is to be written.

Image rotation via jpeg decompression according to an order different from the encoding block scanning order

Abstract: An image processing system that can receive compressed image data corresponding to a representation of an image and process that image data in an order that is independent of the order in which that image data was compressed. A first pass decoding identifies certain 5 information pertaining to the coded units within the compressed image data. Based upon that information, the coded units in the compressed image data may be decoded in an order that is different than the order in which they were encoded, and portions of the image may be rotated by a multiple of 90° independently of other portions of the image, thereby reducing the amount of memory needed to decompress and rotate the compressed image data.

Video receiver/recorder with computer interface

Abstract: AA multiple-media receiver/recorder (1400) comprises a media pathway (1414) capable of carrying media content, one or more media storage elements (1420, 1422, 1424) coupled to the media pathway for storing media content and retrieving media content for performance, a network interface (212, 312), and an emulator (1410). The network interface is capable of accessing media content from a remote source. The emulator can be coupled to the media pathway and capable of directing media flow on the media pathway and reformatting media content in a format unsuitable for performance into a format suitable for performance.

Clock signal generator

Abstract: A clock signal generator for generating clock signals to an integrated circuit. The clock signal generator comprises a delay-locked loop adapted to generate a plurality of mutually delayed clock phases based on a reference clock signal. The delay-locked loop is further adapted to select one of the plurality of clock phases as an output signal of the delay-locked loop in response to a first control signal, wherein said output signal is a first clock signal. The clock signal generator further comprises an inverter arranged to generate an inverse of the output signal and a multiplexer unit arranged to, in response to a clock-invert signal, forward either the output signal or the inverse of the output signal as a second clock signal.