Journal ArticleDOI
Energy-efficient single-clock-cycle binary comparator
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TLDR
A new fast low-power single-clock-cycle binary comparator is presented, which high speed is assured by using parallel-prefix architecture, whereas low power is guaranteed by reducing the switching activities of the internal nodes.Abstract:
A new fast low-power single-clock-cycle binary comparator is presented. High speed is assured by using parallel-prefix architecture, whereas low power is guaranteed by reducing the switching activities of the internal nodes. When implemented with the ST 90 nm 1 V CMOS technology, the proposed circuit exhibits a 4.5 GHz maximum running frequency and 0.77µW/ MHz energy dissipation. Copyright © 2010 John Wiley & Sons, Ltd.read more
Citations
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Journal ArticleDOI
Scalable Digital CMOS Comparator Using a Parallel Prefix Tree
TL;DR: A new comparator design featuring wide-range and high-speed operation using only conventional digital CMOS cells and a regular reconfigurable VLSI topology, which allows analytical derivation of the input-output delay as a function of bitwidth.
Journal ArticleDOI
A 167-ps 2.34-mW Single-Cycle 64-Bit Binary Tree Comparator With Constant-Delay Logic in 65-nm CMOS
TL;DR: A single-cycle tree-based 64-bit binary comparator with constant-delay (CD) logic realized in a 65-nm, 1-V CMOS process is presented in this paper.
Proceedings ArticleDOI
Low Power and High Speed Static CMOS Digital Magnitude Comparators
TL;DR: In this work, a new architecture for magnitude comparators in static logic is presented and the proposed topology presents superior speed performance and reduced power consumption with respect to a state of the art magnitude comparator in the literature.
Journal ArticleDOI
A Low-Power and Area-Efficient 64-Bit Digital Comparator
TL;DR: A new low-power and area-efficient radix-4 tree-based 64-bit digital comparator with 64 XOR-XNOR (XE) blocks that is custom implemented in 90nm 1.2V multi-threshold technology using Cadence-Virtuoso layout editor.
Proceedings ArticleDOI
On the Static CMOS Implementation of Magnitude Comparators
C. Efstathiou,Yiorgos Tsiatouhas +1 more
TL;DR: The proposed comparator architecture is designed in static CMOS logic and compared against the state of the art magnitude comparators in the literature, shows less area overhead, and for small input operands presents lower delay and power-delay product.
References
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Journal ArticleDOI
A Regular Layout for Parallel Adders
TL;DR: It is shown that addition of n-bit binary numbers can be performed on a chip with a regular layout in time proportional to log n and with area proportional to n.
Journal ArticleDOI
High-performance and power-efficient CMOS comparators
Chung-Hsun Huang,Jinn-Shyan Wang +1 more
TL;DR: Post-layout simulation results show that a 64-b comparator designed with the proposed techniques in a 3-V 0.6-/spl mu/m CMOS technology is 16% faster, 50% smaller, and 79% more power efficient as compared with the all-n-transistor comparator, which is the fastest among the conventional comparators.
Journal ArticleDOI
1 GHz 64-bit high-speed comparator using ANT dynamic logic with two-phase clocking
TL;DR: A high-speed 64-bit comparator using two-phase clocking dynamic CMOS logic with modified noninverting all-N-transistor block is presented and detailed simulation results reveal appropriate L/W guidelines for the all- N-transistors block design.
Journal ArticleDOI
A mux -based High-Performance Single-Cycle CMOS Comparator
Hing-mo Lam,Chi-Ying Tsui +1 more
TL;DR: A new architecture for high-fan-in CMOS comparator is proposed, based on a hierarchical two-stage comparator structure and a dynamic MUX is used instead of a comparator in the second stage of the structure to significantly improve the overall delay of the high- fan-in comparators.
Journal ArticleDOI
High-performance single clock cycle CMOS comparator
Hing-mo Lam,Chi-Ying Tsui +1 more
TL;DR: A novel comparison algorithm is introduced, which uses a parallel MSB checking method instead of the traditional priority-encoding based comparison algorithm, which results in significant improvement over the traditional design.