Journal ArticleDOI
A digital CMOS design technique for SEU hardening
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TLDR
In this paper, a new cell design technique is described which may be used to create SEU hardened circuits using actively biased, isolated well transistors to prevent transients in combinational logic from reaching the output node.Abstract:
A new cell design technique is described which may be used to create SEU hardened circuits. The technique uses actively biased, isolated well transistors to prevent transients in combinational logic from reaching the output node.read more
Citations
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Journal ArticleDOI
Radiation-induced soft errors in advanced semiconductor technologies
TL;DR: In this article, the authors review the types of failure modes for soft errors, the three dominant radiation mechanisms responsible for creating soft errors in terrestrial applications, and how these soft errors are generated by the collection of radiation-induced charge.
Journal ArticleDOI
Basic mechanisms and modeling of single-event upset in digital microelectronics
Paul E. Dodd,Lloyd W. Massengill +1 more
TL;DR: Physical mechanisms responsible for nondestructive single-event effects in digital microelectronics are reviewed, concentrating on silicon MOS devices and integrated circuits as discussed by the authors, and the impact of technology trends on single event susceptibility and future areas of concern are explored.
Journal ArticleDOI
Soft errors in advanced computer systems
TL;DR: This article comprehensively analyzes soft-error sensitivity in modern systems and shows it to be application dependent.
Proceedings ArticleDOI
The impact of technology scaling on soft error rate performance and limits to the efficacy of error correction
TL;DR: Memory and logic scaling trends are discussed along with a method for determining logic SER, the soft error rate of advanced CMOS devices, which may limit future product reliability.
Journal ArticleDOI
SEU-sensitive volumes in bulk and SOI SRAMs from first-principles calculations and experiments
Paul E. Dodd,A.R. Shaneyfelt,K.M. Horn,David S. Walsh,G.L. Hash,T.A. Hill,Bruce L. Draper,J.R. Schwank,F.W. Sexton,P.S. Winokur +9 more
TL;DR: In this paper, the authors used 3D simulations, focused ion microscopy, and broadbeam heavy ion experiments to determine and compare the SEU-sensitive volumes of bulk-Si and SOI CMOS SRAMs.
References
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Journal ArticleDOI
Critical evaluation of the pulsed laser method for single event effects testing and fundamental studies
Joseph S. Melinger,S. P. Buchner,Dale McMorrow,W.J. Stapor,Todd R. Weatherford,A.B. Campbell,H. Eisen +6 more
TL;DR: In this article, an evaluation of the pulsed laser as a technique for single events effects (SEE) testing is presented, where the important optical effects, such as laser beam propagation, surface reflection, and linear and nonlinear absorption, determine the nature of laser-generated charge tracks in semiconductor materials.
Journal ArticleDOI
Application of a pulsed laser for evaluation and optimization of SEU-hard designs [CMOS]
TL;DR: In this paper, a quantitative correlation is observed between the laser single-event upset and single event latchup threshold measurements and those performed using accelerator-based heavy ion testing methods, revealing the advantages of incorporating laser evaluation at an early stage into programs described for the development of radiation-hardened parts.
Journal ArticleDOI
An SEU-hardened CMOS data latch design
TL;DR: In this article, a single event-upset hardened CMOS data latch design is described and the hardness is achieved by virtue of the design; thus no fabrication process or design ground-rule development is required.
Journal ArticleDOI
Low power SEU immune CMOS memory circuits
M.N. Liu,S. Whitaker +1 more
TL;DR: In this paper, the authors report a design improvement for CMOS static memory circuits hardened against single event upset (SEU) using a recently proposed logic/circuit design technique, which drastically reduces static power consumption, reduces the number of transistors required in a D flip-flop design, and eliminates the possibility of capturing an upset state in the slave section during a clock transition.
Journal ArticleDOI
SEU hardened memory cells for a CCSDS Reed-Solomon encoder
S. Whitaker,J. Canaris,K. Liu +2 more
TL;DR: A design technique to harden CMOS memory circuits against single event upset (SEU) in the space environment is reported and a RAM cell and flip-flop design are presented to demonstrate the method.
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