Journal ArticleDOI
A New Solution for Superjunction Lateral Double Diffused MOSFET by Using Deep Drain Diffusion and Field Plates
Zhi Lin,Xingbi Chen +1 more
TLDR
In this article, a new solution based on the concept of a deep drain diffusion combined with field plates (FPs) is proposed for the superjunction lateral double diffused MOSFET (SJ-LDMOS) device.Abstract:
A new solution based on the concept of a deep drain diffusion combined with field plates (FPs) is proposed for the superjunction lateral double diffused MOSFET (SJ-LDMOS) device. The deep drain diffusion suppresses the curvature effect of the conventional SJ-LDMOS and the FPs optimize the electric field distribution further. Simulated results show that the proposed SJ-LDMOS exhibits figure of merits of 12.8 and 8.5 MW/cm $^{\mathrm{{2}}}$ for 700 and 1200 V ratings, respectively, which are about 20% better than the prior art. Moreover, the proposed SJ-LDMOS is less sensitive to the charge imbalance. Using the isotropic etch technique followed by implantation, the deep drain diffusion is easy to be fabricated.read more
Citations
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Journal ArticleDOI
Si/SiC heterojunction lateral double-diffused metal oxide semiconductor field effect transistor with breakdown point transfer (BPT) terminal technology
TL;DR: In this article, a Si on silicon carbide (SiC) lateral double-diffused metal oxide semiconductor field effect transistor with deep drain region is proposed, which transfers the breakdown point and utilises the high critical electric field of SiC material to suppress the curvature effect of the drain, which eventually alleviates the trade-off relationship between breakdown voltage and specific on-resistance.
Proceedings ArticleDOI
A variation laterl doping layer and lightly doped region compensated superjunction LDMOS
TL;DR: In this paper, a new solution based on the concept of a variation lateral doping (VLD) compensated layer and a lightly doped region (LDR) is proposed for the superjunction lateral double diffused MOSFET (SJ-LDMOS).
Journal ArticleDOI
Analytical Study on a 700 V Triple RESURF LDMOS With a Variable High- K Dielectric Trench
Zhen Cao,Qian Wang,Licheng Jiao +2 more
TL;DR: In this paper, a triple REduced SURface field (RESURF) lateral double-diffused MOSFET with variable high-VHK dielectric trench for smart power applications is proposed and studied by TCAD simulations.
Journal ArticleDOI
Improving breakdown performance for SOI LDMOS with sidewall field plate
TL;DR: In this article, a silicon-on-insulator (SOI) lateral diffused MOSFET (LDMOS) incorporated with sidewall field plate (SEP) is presented and investigated using three-dimensional numeric simulation.
Journal ArticleDOI
A 600-V Super-Junction pLDMOS Utilizing Electron Current to Enhance Current Capability
TL;DR: In this paper, a super-junction p-type lateral diffused metal-oxide-semiconductor transistor (SJ-pLDMOS) utilizing electron to enhance the current capability is proposed.
References
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Power Semiconductor Devices
Jerry Hudgins,Rik W. De Doncker +1 more
TL;DR: In this paper, the authors proposed a matrix of on-off switches to convert power from ac-to-dc (rectifier), dc-todc (chopper), dc to ac (inverter), and ac to ac at the same (ac controller) or different frequencies (cycloconverter).
Journal ArticleDOI
Sj/resurf ldmost
TL;DR: In this paper, a monolithic lateral double diffused MOSFET based on the super junction (SJ) concept is proposed to significantly improve the device's on-state and off-state characteristics.
Journal ArticleDOI
Super-junction LDMOST on a silicon-on-sapphire substrate
S.G. Nassif-Khalil,C.A.T. Salama +1 more
TL;DR: In this article, a super-junction lateral double diffused MOST (SJ-LDMOST) in silicon-on-sapphire technology targeting power integrated circuits (PICs) is proposed, implemented and characterized.
Proceedings ArticleDOI
Lateral unbalanced super junction (USJ)/3D-RESURF for high breakdown voltage on SOI
TL;DR: In this paper, the authors examined the possibility of the Super Junction (SJ) concept to realize lateral device structures on SOI with high breakdown voltage and low on-resistance for use in power integrated circuits (PICs).