Proceedings ArticleDOI
A Novel Monitoring Method of RF Characteristics Variations for Sub-0.1μm MOSFETs with Precise Gate-resistance Model
A. Tanabe,K. Hijioka,Yoshihiro Hayashi +2 more
- pp 725-728
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TLDR
A new RF gate resistance model with a silicide-polysilicon interface resistance is a key factor to estimate the RF characteristics precisely and is effective in monitoring RF characteristics and their variations for scaled-down, RF/mixed-signal circuits at the chip fabrication.Abstract:
RF characteristics for sub-0.1μm MOSFETs such as fT, fmax and their variations are estimated from the DC and capacitance parameters. A new RF gate resistance model with a silicide-polysilicon interface resistance is a key factor to estimate the RF characteristics precisely. The variations of RF characteristics are also inferred from correlation coefficient between the RF parameters and the DC and capacitance parameters. This method is effective in monitoring RF characteristics and their variations for scaled-down, RF/mixed-signal circuits at the chip fabrication.read more
Citations
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Journal ArticleDOI
Investigation of Parasitic Effects and Design Optimization in Silicon Nanowire MOSFETs for RF Applications
TL;DR: In this paper, the design of silicon nanowire MOSFETs for RF applications is discussed based on 3D simulation, including the impacts of the parasitic capacitances and resistance.
Journal ArticleDOI
Characterization and Modeling of RF-Performance $(f_{T})$ Fluctuation in MOSFETs
TL;DR: In this article, the fluctuation of RF performance (particularly for fT: cutoff frequency) in the transistors fabricated by 90-nm CMOS technology has been investigated, and the model is well fitted with the measurement data within approximately 1% error.
Patent
Modeling gate resistance of a multi-fin multi-gate field effect transistor
TL;DR: In this article, a multi-fin multi-gate field effect transistor (MUGFET) is modeled as a gate structure with a horizontal portion traversing multiple semiconductor fins and comprising a plurality of first resistive elements connected in series, with vertical portions adjacent to opposing sides of the semiconductor fin and comprising second resistive element connected in parallel by the horizontal portion.
Proceedings ArticleDOI
A novel small capacitance RF-MOSFET with small-resistance Long-finger Gate Electrode
TL;DR: In this article, a small capacitance RF-MOSFET with small-resistance long-finger gate electrode, which is featured by Direct Finger Contact (DFC) on the gate electrode in active region to reduce its resistance.
Proceedings ArticleDOI
45nm PD SOI FET gate resistance optimization for mmw applications
TL;DR: In this article, the impact of phosphorous polysilicon gate pre-doping and silicide thickness on the gate resistance of NFETs was investigated on a 45nm partially depleted (PD) Silicon-on-Insulator (SOI) technology with a Ni silicided poly SiON gate stack.
References
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Journal ArticleDOI
A New Method to Determine Effective MOSFET Channel Length
Kazuo Terada,Hiroki Muta +1 more
TL;DR: In this paper, an accurate and convenient method to determine an effective MOSFET channel length is proposed based on a computer aided evaluation of an intrinsic channel resistance without using special test devices.
Journal ArticleDOI
Overlooked interfacial silicide-polysilicon gate resistance in MOS transistors
TL;DR: In this paper, a previously overlooked gate resistance component in silicided polysilicon-gate metal-oxide-semiconductor field effect transistors (MOSFETs) is discussed.
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