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Title
A single-inductor switching DC-DC converter with five outputs and ordered power-
distributive control
Permalink
https://escholarship.org/uc/item/7541n5fq
Journal
IEEE Journal of Solid-State Circuits, 42(12)
ISSN
0018-9200
Authors
Le, Hanh-Phuc
Chae, Chang-Seok
Lee, Kwang-Chan
et al.
Publication Date
2007-12-01
DOI
10.1109/JSSC.2007.908767
Peer reviewed
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University of California
2706 IEEE JOURNAL OF SOLID-STATE CIRCUITS, VOL. 42, NO. 12, DECEMBER 2007
A Single-Inductor Switching DC–DC Converter With
Five Outputs and Ordered Power-Distributive Control
Hanh-Phuc Le, Student Member, IEEE, Chang-Seok Chae, Student Member, IEEE,
Kwang-Chan Lee, Student Member, IEEE, Se-Won Wang, Student Member, IEEE, Gyu-Ha Cho, and
Gyu-Hyeong Cho, Member, IEEE
Abstract—An integrated five-output single-inductor mul-
tiple-output dc-dc converter with ordered power-distributive
control (OPDC) in a 0.5
m Bi-CMOS process is presented. The
converter has four main positive boost outputs programmable
from
+
5Vto
+
12 V and one dependent negative output ranged
from
12 V to 5 V. A maximum efficiency of 80.8% is achieved
at a total output power of 450 mW, with a switching frequency
of 700 kHz. The performance of the converter as a commercial
product is successfully verified with a new control method and
proposed circuits, including a full-waveform inductor-current
sensing circuit, a variation-free frequency generator, and an
in-rush-current-free soft-start method. With simplicity, flexi-
bility, and reliability, the design enables shorter time-to-market
in future extensions with more outputs and different operation
requirements.
Index Terms—Ordered power-distributive control (OPDC),
single-inductor multiple-output (SIMO) converter, soft-start,
zero-current sensor.
I. INTRODUCTION
A
DC–DC converter has been an indispensable part of many
power-management systems. Its importance is gaining
more and more attention when the trend of voltage scaling is
not only limited to digital circuits [1], [2], but also spreading
to other applications, one of which is the emerging active-
matrix OLED (AM-OLED) display panels of upcoming cel-
lular phones and other portable devices [3]. As all designers
put effort into size reduction, a converter with different output
voltages cannot stay out of that trend, forcing designers to
find a method to shrink the size in both on-chip and off-chip
implementations. Of all of the approaches, single-inductor
multiple-output (SIMO) converters come to prevail. SIMO con-
verters can support more than one output while requiring only
one off-chip inductor, promising many appealing advantages,
in particular the reduction of bulky power devices, including
Manuscript received April 19, 2007; revised August 7, 2007. This work was
supported by KEC and JDA of Korea.
H.-P. Le was with the Korea Advanced Institute of Science and Technology
(KAIST), Daejeon 305-701, Korea. He is now with the Department of Electrical
Engineering and Computer Sciences, University of California, Berkeley, CA
94720-1772 USA (e-mail: phucle@eecs.berkeley.edu).
C.-S. Chae, K.-C. Lee, S.-W. Wang, and G.-H. Cho are with the Circuit Design
and System Application Laboratory, Department of Electrical Engineering and
Computer Science, Korea Advanced Institute of Science and Technology, Dae-
jeon 305-701, Korea (e-mail: suggy35@kaist.ac.kr; lionkinglkc@kaist.ac.kr;
wangse@kaist.ac.kr; ghcho@ee.kaist.ac.kr).
G.-H. Cho is with JDA Technology Company, Ltd., Daejeon 305-701, Korea
(e-mail: ghcho@hanmail.net).
Digital Object Identifier 10.1109/JSSC.2007.908767
Fig. 1. One boost and
n
0
1
LDOs.
inductors, capacitors, and control ICs. The cost of mass produc-
tion, hence, is remarkably reduced, and SIMO therefore shows
up as the most suitable and cost-effective solution in the future
development of dc–dc converters, attracting many producers
with various applications in portable devices. However, it is
still a big challenge to dc–dc converter designers to find the
best method of the implementation of this converter type.
The topology that has been frequently used by many de-
signers and manufacturers is shown in Fig. 1. With this topology
to make
outputs, one boost converter is used together with
low drop-out (LDO) converters [4]. Although incorporates
advantages of the LDO design, which are simplicity, low output
ripple, and short time-to-market, the topology is not appropriate
for future development owing to the main disadvantages of
LDOs, including low efficiency and area consumption by serial
power switches.
Most recently, a switching single-inductor dual-output
(SIDO) boost converter has been reported in [5] and [6]. The
SIDO converter, shown in Fig. 2, works in pseudocontinuous
or discontinuous conduction mode (PCCM/DCM) with a
freewheel period, trying to handle large load currents and
eliminate cross-regulation. However, PCCM operation un-
necessarily dissipates energy in the resistance of the inductor
and freewheel-switch because of the nonzero inductor current
during the freewheel time, illustrated in Fig. 3, which reduces
the overall efficiency. More disadvantageously, using separate
proportional-integral (P-I) compensators and output-switch
current sensors for the outputs with time-multiplexing con-
trol causes unwanted complexity and increases the chip area.
Therefore, PCCM/DCM is not a good solution, especially when
the number of outputs increases.
The drawbacks of these conventional approaches, therefore,
urge the development of a new SIMO converter, which can re-
duce area consumption while maintaining good regulations for
0018-9200/$25.00 © 2007 IEEE
LE et al.: SINGLE-INDUCTOR SWITCHING DC–DC CONVERTER WITH FIVE OUTPUTS AND OPDC 2707
Fig. 2. Architecture of the PCCM SIDO dc–dc converter.
Fig. 3. Loss in the PCCM SIDO dc–dc converter.
outputs. The converter should also work properly in DCM and
CCM. In addition, it is desirable to have a new control method
of simplicity and flexibility in implementation that can be ap-
plied to different converter types of multiple-output topologies
for different application requirements.
In this paper, we present an integrated SIMO dc–dc converter,
fabricated in a 0.5
m Bi-CMOS technology. Employing a
novel ordered power-distributive control (OPDC), which will
be introduced in Section II, the SIMO converter can regulate
four main programmable positive boost outputs and one depen-
dent negative output developed by a charge-pump. Important
proposed circuits and techniques, including inductor-current
sensor, frequency generator, soft-start method, dead-time
control, and cross-regulation, are discussed and verified in
Section III. In Section IV, experimental results will be provided
to prove the OPDC and the performance of the converter.
Section V will present the future extensions of the design, and
conclusions will be made in Section VI.
II. SIMO C
ONVERTER
WITH FIVE OUTPUTS
A. Architecture and OPDC for Boost Outputs
The architecture of the five-output SIMO converter sug-
gested in this paper is shown in Fig. 4. The OPDC arranges
four boost outputs Vo1, Vo2, Vo3, and Vo4 in descending
order of priority to, one by one, share the charge from the in-
ductor in every switching cycle or, more correctly, every power
distribution cycle. The first three output voltages Vo1, Vo2,
and Vo3 are controlled using comparators and are thus called
comparator-controlled outputs, while the last-ordered output
Vo4 is P-I controlled with an error amplifier that is responsible
Fig. 4. Architecture of the proposed OPDC SIMO dc–dc converter.
for the converter’s total charge. Therefore, in this OPDC, all of
the errors of the preceding comparator-controlled outputs are
transferred and accumulated to the last, which is the only one
requiring a compensation network in the feedback loop.
The operating principle of OPDC can best be explained using
the timing diagram in Fig. 5, where the high part of the signal Si
represents the on-state of the switch Si. During the time denoted
DT, the inductor current
ramps up at a rate of . The
duty-cycle D is determined by peak-current mode control. The
four output switches S1, S2, S3, S4 and the freewheel switch
Sf (which is active in DCM), in order, turn on during the time
, where . During , ramps down with
different slopes depending on the output voltages and switching
sequence. S1 is on at the beginning of
, making ramp
down at a rate of
and flow into Vo1. As soon as
comparator CP1 detects that Vo1 is larger than its target voltage,
expires, S1 is turned off, and S2 is turned on. The same
sequence then repeats as the inductor current ramps down with
a slope equal to
Vo 2 during , then Vo 3
during , while Vo2 and then Vo3, in turn, get the
second and third portions of charge, respectively. Switch S4 is
the last output switch to turn on, and the last portion of charge
flows into Vo4 while the slope of the inductor current is
Vo 4
during . When the inductor current is zero,
expires, S4 is off, and Sf turns on during to short the two
ends of the inductor and suppress possible ringing at Vx until
the end of the switching cycle. In this mode of operation, the
converter is said to work in DCM. Since
does not decrease
to zero in CCM operation, there is no freewheel period, which is
indicated by
, as illustrated by . Dependent on the last
portion of charge, the loop containing Vo4 and the total current
loop are compensated and controlled by the well-known peak-
current control method. These control loops guarantee that the
last portion of charge is enough to keep channel 4 at its target
voltage, while good voltage regulation is already maintained in
the preceding outputs Vo1, Vo2, and Vo3.
2708 IEEE JOURNAL OF SOLID-STATE CIRCUITS, VOL. 42, NO. 12, DECEMBER 2007
Fig. 5. Timing diagram of the OPDC SIMO dc–dc converter.
B. Dependent Negative Output With a Charge-Pump
The charge-pump circuit included in Fig. 4 with two Schottky
diodes and two capacitors is connected to the node Vx and
makes a negative output from the voltage changes at Vx. The
flying capacitor
gets charge when the positive outputs get
energy and Vx goes high and then transfers negative charge to
the output capacitor
when the switch Sx is on and Vx
goes low. The negative output voltage, therefore, depends on
the voltage drop over the Schottky diodes
and the highest
positive output voltage, which is Vo1 in this design,
Vo 1 . Since good regulation is not necessary in the neg-
ative output, feedback control is not added, and
is chosen
sufficiently small to have no effect on the total operation and
dead-time control.
C. OPDC and Switching Flexibility
The simplicity and flexibility of the OPDC, with three voltage
comparators for the three preceding outputs and one P-I control
for the last output, prove that the converter can have different
switching patterns in regulating the outputs, as shown in Fig. 5.
shows the case of CCM operation where three or two
output switches are orderly and alternately on in one switching
cycle. Operation at the boundary of CCM and DCM and one
in DCM are illustrated with
and , respectively. It
is worth noting that OPDC allows that the turn-on frequency
and the duty
of an output switch do not always have to be
constant, provided that the output voltage be regulated. How-
ever, the principle of OPDC is always sustained in that the total
charge from the inductor is, one by one, distributed to four boost
outputs Vo1, Vo2, Vo3, and Vo4 in descending order of priority
in every power distribution cycle. One power distribution cycle
is said to end when the last output Vo4 gets its portion of charge.
III. C
IRCUITS AND IMPLEMENTATIONS
The converter has important blocks, as shown in Fig. 4. The
reference voltages are programmed from off-chip digital sig-
nals. The function of the logic order control block is to pass the
signals from comparators in order of priority to make OPDC.
Since Vo1 is always set to the highest voltage, it is used to bias
Fig. 6. Peak-inductor-current sensor.
Fig. 7. Zero-inductor-current sensor.
all of the bodies of pMOS power transistors and supply all gate
drivers for power transistors.
A. Full-Waveform Inductor–Current Sensor
The implementation of current-mode control schemes
described in [7] and [8] requires sensing of the complete wave-
forms of inductor current, including the peak- and zero-current
information of the inductor–current waveform. The design
challenge arising from such inductor current sensing is not
completely overcome, but usually overlooked, especially in
dc–dc step-up converters. Some published solutions [9], [10]
only focus on sensing inductor current in nMOS turn-on
time, while current sensing in pMOS turn-on time is usually
omitted by using only CCM operation. However, DCM oper-
ation is often required for light-load outputs with maintained
low-output voltage ripple; otherwise, inductor values need to
be big.
A current sensor, which can sense complete waveforms of in-
ductor current, is proposed in this paper with two partial sensors
to achieve both the peak- and the zero-current information.
1) Peak-Current Sensor: The circuit of an accurate peak-in-
ductor-current sensor is illustrated in Fig. 6. The circuit is de-
signed to sense the inductor current waveform in the charge pe-
riod through the drain–source voltage over the on-resistance of
the main switch Sx of the converter when it is on. The current in-
formation in the form of the drain–source voltage is transferred
LE et al.: SINGLE-INDUCTOR SWITCHING DC–DC CONVERTER WITH FIVE OUTPUTS AND OPDC 2709
Fig. 8. Measured waveforms of current sensor (a) in DCM and (b) in CCM.
through a – converter composed of amplifier A1, transistor
M5, and resistor R1, then mirrored via the 1:1 current mirror
M3-M4, and, finally, appears at node Peak_current in the form
of voltage over R2. The gain of this sensor, therefore, is deter-
mined by the ratio R2/R1. A small positive offset
, which is
given at the positive input of A1, is saved and then cancelled at
output by capacitor
and . The intentional positive offset
and offset cancellation technique are proposed in this cir-
cuit to eliminate any possible offset at A1 inputs and improve
the performance. M7 is inserted as shown in this circuit to re-
move the charge injection errors that can be seen at the output
when M6 is turned off.
2) Zero-Current Sensor: Zero-inductor-current sensing is
necessary to enable DCM operation when the converter sup-
plies light loads. In conventional techniques [5], [6], detecting
zero-inductor current through the on-resistance of output pMOS
switches causes unnecessary complexity and area consumption,
especially when the number of outputs of SIMO step-up dc-dc
converters and output voltages are increased. Moreover, in
this OPDC, the switching flexibility of output power switches
requires a new zero-inductor-current sensor that can work with
any switching sequence and different programmable output
voltages.
A novel precise zero-inductor-current sensor is shown in
Fig. 7. The core idea of this circuit lies in the fact that, in a
dc–dc converter, inductor current waveforms are formed by a
fixed inductor value and the voltage differences between the
two terminals of the inductor. The AC_current signal is thus
correlatively generated with a constant
and the said voltage
differences. With this approach, the AC_current signal has
the same shape as the real inductor current waveform, thus
enabling zero-inductor-current detection. This circuit is also
called a current observer, as it precisely detects a zero-inductor
current without difficulties in sensing online current through
output pMOS switches. More details of this circuit are reported
in [11].
3) Experimental Results of the Current Sensor: The experi-
mental results in Fig. 8(a) and (b) show that the proposed cir-
cuit of the full current sensor, including peak-current sensor
(or nMOS current sensing) and zero-current sensor (through
AC-current signal), works correctly and as designed. The cir-
cuit of the full-waveform current sensor can be applied partially
or fully in different converters with its simplicity and reliability.
Fig. 9. Frequency generator.
Fig. 10. In-rush-free soft-start.
B. Frequency Generator
The circuit in Fig. 9 is one modification from that reported
in [12]. The triangular signal at the
node is formed by two
predetermined slopes and limited within
to , where
. The currents , , and are proportional
to the current
. The ramp-up and ramp-down
slopes of
are and . The triangular voltage
is arranged to always be chasing the voltage at the posi-
tive input of the hysteretic comparator CP, which is switched
between
and periodically by the output of the com-
parator. The output of the comparator, in fact, is used to make
the main clock and one-shot signal for PWM operation of the
converter. The maximum duty cycle of the main nMOS switch
Sx, determined by the ratio of
and , is about 85% in this
design. The triangular signal is used to make the slope compen-
sation for peak-current-mode control [7], [8].
