Proceedings ArticleDOI
An automated tool for chip-scale ESD network exploration and verification
Benjamin Viale,Mathieu Fer,Lionel Courau,Philippe Galy,Blaise Jacquier,J. Lescot,Bruno Allard +6 more
- pp 1-10
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TLDR
ESD IP Explorer as mentioned in this paper is a tool for full-chip static ESD (ElectroStatic Discharge) verification on 28nm UTBB (Ultra-thin-body and BOX-Buried Oxide) FD-SOI High-K metal gate technology.Abstract:
This paper describes a tool for full-chip static ESD (ElectroStatic Discharge) verification called ESD IP Explorer. The tool feasibility is first demonstrated on a 64-pin custom R&D testchip. Its scalability is tested in a second example involving a 138mm² 3,066-bump prototype, which basic verification is performed in less than 8 hours. Both examples are in 28nm UTBB (Ultra-thin-body and BOX — Buried Oxide) FD-SOI High-K metal gate technology. More advanced static verification features are finally discussed.read more
Citations
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Journal ArticleDOI
A Standalone Graph-Theory Based Tool for Full-Chip ESD Verification
TL;DR: In this article , a flow of the automatic electrostatic discharge (ESD) verification is presented, a basic overview of the most important methodology steps is shown, with more detailed explanation of breaking voltage (BV) model generation.
Peer ReviewDOI
A Standalone Graph-Theory Based Tool for Full-Chip ESD Verification
TL;DR: In this article , a flow of the automatic electrostatic discharge (ESD) verification is presented, and a basic overview of the most important methodology steps is shown, with more detailed explanation of breaking voltage (BV) model generation.
Journal ArticleDOI
On the need for a new ESD verification methodology to improve the reliability of ICs in advanced 28nm UTBB FD-SOI technology
TL;DR: The proposed solution is used to limit the risk of ESD design errors and to enhance IC reliability, independently of the implemented ESD protection strategy and the type of package assembly technique.
References
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Book
Applied Regression Analysis
Norman R. Draper,Harry Smith +1 more
TL;DR: In this article, the Straight Line Case is used to fit a straight line by least squares, and the Durbin-Watson Test is used for checking the straight line fit.
Drawing graphs with dot
TL;DR: Graphdot draws directed graphs as hierarchies with well-tuned layout algorithms for placing nodes and edge splines, edge labels, “record” shapes with “ports” for drawing data structures; cluster layouts; and an underlying file language for stream-oriented graph tools.
Proceedings Article
Automatic layout based verification of electrostatic discharge paths
TL;DR: In this paper, an ESD path verification methodology based on layout parasitic extraction is proposed to improve the robustness of a 0.5 um BiCMOS design to improve its ESD robustness.
Proceedings ArticleDOI
BIMOS transistor and its applications in ESD protection in advanced CMOS technology
Ph. Galy,Jean Jimenez,Johan Bourgeat,Alexandre Dray,Ghislain Troussier,Boris Heitz,Nicolas Guitard,D. Marin-Cudraz,H. Beckrich-Ros +8 more
TL;DR: This paper introduces the BIMOS ESD approach with simulations in 45nm with Silicon measurements performed on 32 nm CMOS high k metal gate.