Journal ArticleDOI
An eighth-order CMOS low-pass filter with 30-120 MHz tuning range and programmable boost
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TLDR
In this article, a low-pass filter with programmable boost is presented, realized as a cascade of biquad and first-order cells, implemented in a 0.25-/spl mu/m 2.5-V CMOS technology.Abstract:
A CMOS low-pass filter with programmable boost is presented. The architecture is a G/sub m//C type with the G/sub m/ value controlled through a resistor servo approach. The transfer function has been optimized in order to reduce the sensitivity to component parameter variations. The 1:4 tuning range is achieved by exploiting a dual-loop control over a degenerated differential pair. At the nominal output voltage swing of 200 mV/sub pp/ differential, a THD better than 40 dB is guaranteed. The high-frequency boost is programmable between 6 and 14 dB. This filter, realized as a cascade of biquad and first-order cells, is implemented in a 0.25-/spl mu/m 2.5-V CMOS technology. It dissipates 120 mW with f/sub c/=120 MHz and has a die area of 0.23 mm/sup 2/.read more
Citations
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Proceedings Article
Flexible baseband analog circuits for software-defined radio front-ends
TL;DR: A novel approach to design a digitally programmable low pass filter and variable gain amplifier intended for a software-defined radio (SDR) front-end that is able to set performance parameters like cut-off frequency, selectivity, noise, and gain guaranteeing at any time a near-optimal power/performance trade-off.
Journal ArticleDOI
Flexible Baseband Analog Circuits for Software-Defined Radio Front-Ends
TL;DR: In this article, the authors present an approach to design a digitally programmable low pass filter (LPF) and variable gain amplifier (VGA) intended for a software-defined radio (SDR) front-end.
Book
CMOS Analog Design Using All-Region MOSFET Modeling
TL;DR: In this paper, a design approach based on a MOSFET model valid for all operating regions, rather than the standard square-law model, is presented, with numerous design examples and exercises also included.
Journal ArticleDOI
A 60-mW 200-MHz continuous-time seventh-order linear phase filter with on-chip automatic tuning system
TL;DR: In this paper, a full CMOS seventh-order linear phase filter based on g/sub m/-C biquads with a -3dB frequency of 200 MHz is realized in 0.35/spl mu/m CMOS process.
Journal ArticleDOI
A G/sub m/-C low-pass filter for zero-IF mobile applications with a very wide tuning range
TL;DR: In this paper, a third-order G/sub m/-C Butterworth low-pass filter is proposed for zero-IF radio receiver architecture for multimode mobile communications, with a cutoff frequency range from 50 kHz to 2.2 MHz.
References
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Journal ArticleDOI
A 4-MHz CMOS continuous-time filter with on-chip automatic tuning
Francois Krummenacher,N. Joehl +1 more
TL;DR: This paper presents a 3rd order low-pass continuous-time filter with 4 MHz cut-off frequency, integrated in a 3 μm CMOS process, based on the direct simulation of a doubly-terminated LC ladder using capacitors and fully-balanced, current-controlled transconductance amplifiers with extended linear range.
Proceedings Article
A 4-MHz CMOS Continuous-Time Filter with On-Chip Automatic Tuning
Francois Krummenacher,N. Joehl +1 more
TL;DR: In this article, a 3rd order low-pass continuous-time filter with 4 MHz cut-off frequency, integrated in a 3?m CMOS process, is presented, based on direct simulation of a doublyterminated LC ladder using capacitors and fully-balanced, current-controlled transconductance amplifiers with extended linear range.
Journal ArticleDOI
Widely programmable high-frequency continuous-time filters in digital CMOS technology
TL;DR: In this paper, the authors present design considerations for programmable high-frequency continuous-time filters implemented in standard digital CMOS processes, where accumulation MOS capacitors are used as integrating elements to reduce area, and a constant-capacitance scaling technique is employed to ensure that even parasitic capacitances remain invariant when transconductors are switched in and out of the filter.
Journal ArticleDOI
A 20-MHz sixth-order BiCMOS parasitic-insensitive continuous-time filter and second-order equalizer optimized for disk-drive read channels
C.A. Laber,Paul R. Gray +1 more
TL;DR: A fast parasitic-insensitive continuous-time filter and equalizer integrated circuit that uses an active integrator that is optimized to limit high-frequency noise and to amplitude equalize the data pulses in hard disk read-channel systems is described.
Journal ArticleDOI
A broad-band tunable CMOS channel-select filter for a low-IF wireless receiver
TL;DR: In this article, the authors describe a filter designed for a wideband wireless LAN receiver operating in the 2.4-2.48 GHz ISM band, where linearity is specified as out-of-band 3rd order intercept (IP3), to limit the in-band intermodulation from large interferers lying in the filter stop band.