An inductive down converter system-in-package for integrated
power management in battery-powered applications
Citation for published version (APA):
Bergveld, H. J., Karadi, R., & Nowak, K. (2008). An inductive down converter system-in-package for integrated
power management in battery-powered applications. In
Proc. IEEE Power Electronics Specialist Conference
(PESC 2008, Rhodes, 15-19 June 2008)
(pp. 3335-3341). Institute of Electrical and Electronics Engineers.
https://doi.org/10.1109/PESC.2008.4592470
DOI:
10.1109/PESC.2008.4592470
Document status and date:
Published: 01/01/2008
Document Version:
Publisher’s PDF, also known as Version of Record (includes final page, issue and volume numbers)
Please check the document version of this publication:
• A submitted manuscript is the version of the article upon submission and before peer-review. There can be
important differences between the submitted version and the official published version of record. People
interested in the research are advised to contact the author for the final version of the publication, or visit the
DOI to the publisher's website.
• The final author version and the galley proof are versions of the publication after peer review.
• The final published version features the final layout of the paper including the volume, issue and page
numbers.
Link to publication
General rights
Copyright and moral rights for the publications made accessible in the public portal are retained by the authors and/or other copyright owners
and it is a condition of accessing publications that users recognise and abide by the legal requirements associated with these rights.
• Users may download and print one copy of any publication from the public portal for the purpose of private study or research.
• You may not further distribute the material or use it for any profit-making activity or commercial gain
• You may freely distribute the URL identifying the publication in the public portal.
If the publication is distributed under the terms of Article 25fa of the Dutch Copyright Act, indicated by the “Taverne” license above, please
follow below link for the End User Agreement:
www.tue.nl/taverne
Take down policy
If you believe that this document breaches copyright please contact us at:
openaccess@tue.nl
providing details and we will investigate your claim.
Download date: 09. Aug. 2022
3335
An Inductive Down Converter System-in-
Package for Integrated Power Management in
Battery-powered Applications
H.J. Bergveld, R. Karadi and K. Nowak
NXP Semiconductors, Corporate Innovation & Technology, Research, Department Mixed-Signal Circuits and Systems,
High Tech Campus 37, 5656 AE, Eindhoven, the Netherlands, HenkJan.Bergveld@nxp.com
Abstract—With the increasing number of voltage
conversions that have to be efficiently implemented in a
mobile device, the PCB space occupied by switched-mode
DC-DC converters with external passive components will
become unacceptably high. Therefore, a clear need exists for
small-form-factor high-efficiency DC-DC converters having
the necessary passive components integrated within one
package. This will enable the integration of a DC-DC
converter with the load and consequently the system
integration of power management. This paper describes the
measurement results of an integrated inductive down
converter, where the active electronics (power stage and
driver circuitry) has been implemented in 0.18-μ
μμ
μm CMOS
technology and the passive components (output LC filter
and decoupling capacitor) have been implemented in a state-
of-the-art proprietary passive-integration process
technology using high-density trench-MOS capacitors (80
nF/mm
2
) and an 8-μ
μμ
μm thick copper top metallization layer.
The active die of the converter has been flip-chipped on top
of the passive die to reduce parasitic component values. This
yields a System-in-Package (SiP) that achieves a step-down
DC-DC conversion without any external components. Due to
the limited inductance achievable with the used planar air
coil in the acceptable area, the switching frequency of the
DC-DC converter has been increased. At the same time,
Zero-Voltage-Switching (ZVS) measures have been
implemented to reduce the switching losses at this increased
frequency. A maximum efficiency of 65% at 80 MHz has
been achieved for an input voltage of 1.8 V, an output
voltage of 1.1 V and an output current of 100 mA. After
explaining the motivation behind integrated power
management and the choice for an integrated inductive
converter, this paper describes the main design aspects of
the realized integrated inductive DC-DC down converter.
Next, it presents some details of the used passive-integration
process, the design of the passive die including the LC filter
and the construction of the SiP. Finally, the measurement
results of the converter are discussed and conclusions are
drawn.
I. I
NTRODUCTION
The number of features implemented in mobile devices
increases dramatically leading to a multitude of different
supply voltages, all of which need to be generated from a
single battery voltage. For example, the current invasion
of solid-state lighting applications, such as LED flash
allowing improved photo quality, leads to different
voltage and current requirements than other applications
and therefore necessitates the addition of DC/DC
converters to the system. At the same time, the continuous
drive towards better autonomy has led to the use of
voltage islands in digital ICs. In each voltage island the
lowest possible supply voltage is used to run the
connected digital circuitry at the optimum efficiency. This
is commonly referred to as voltage scaling and leads to
even more different supply voltages that need to be
independently generated from the battery voltage [1].
For optimum efficiency, especially larger voltage
differences need to be converted by switched-mode DC-
DC converters, including capacitive and inductive DC/DC
converters. Linear regulators yield unacceptably low
efficiencies in this case. Capacitive converters have the
advantage of not needing an inductor, which is often
costly and bulky, but the control of the output voltage over
input-voltage variations is limited since the voltage-
conversion ratio is determined by the circuit topology. A
possible solution to this problem is to vary the effective
output resistance of the converter, e.g. by changing the
duty cycle at which the switches are addressed, but this
substantially decreases efficiency when the input-voltage
range is relatively large [2]. For a large input-voltage
range, which appears in all targeted mobile applications
using a Li-ion battery, the alternative solution to maintain
output-voltage regulation and acceptable efficiency is to
implement multi-ratio capacitive converters where the
appropriate ratio is chosen dependent on the input voltage
and load requirements [3],[4]. However, in order to
optimize the average efficiency over the input-voltage
range the number of ratios may become rather high,
leading to a relatively large number of capacitors.
Inductive DC-DC converters are attractive, since they
enable good control of the output voltage over input-
voltage and output-load variations by means of controlling
the duty cycle of the power switches using only three
passive components. Two capacitors are used for input
decoupling and output filtering, respectively, and one
inductor is used for energy transfer from input to output.
Both in the case of capacitive and inductive DC-DC
converters, however, using external passive components
to accommodate the increasing number of voltage
conversions would lead to unacceptably high volume and
cost. Therefore, the need arises for small-form-factor
highly efficient DC-DC converters with package-
integrated passive components. This enables integration of
the DC-DC converter with the load, and, consequently, the
system integration of power management. As mentioned
above, inductive DC-DC converters are better able to
978-1-4244-1668-4/08/$25.00 ©2008 IEEE
3336
V
in
V
out
C
out
L
LX
I
L
C
in
C
x
V
g,P
V
g,N
V
g
V
LX
I
L
V
in
V
in
V
g,P
V
g,N
P ON N ON
Δ
I
t
t
t
Figure 1. General block diagram of a synchronous DC-DC down
converter with corresponding waveforms
handle the relatively large input-voltage range in Li-ion-
battery-powered applications with a relatively low number
of passive components. Since the voltage of the
commonly used Li-ion battery is typically larger than the
supply voltages for the ICs in a mobile device, this paper
therefore focuses on integrated inductive down converters.
Air-core inductors are popular for realizing integrated
inductors due to their relatively simple structure and good
integration possibilities [5]-[8]. Since the required small
volume and the low permeability of air limit the
achievable inductance value, the switching frequency of
the DC-DC converters has to be increased
correspondingly, leading to low efficiencies without
proper measures. The use of multiple air-core inductors in
multi-phase Voltage-Regulator Module (VRM)
applications has shown that efficiencies between 72% and
84% are possible for switching frequencies of 480 MHz
and 100 MHz, respectively, for output powers above 10 W
[5],[6]. However, for mobile applications the required
output powers are much lower, complexity should be low
and the height of SMD inductors inside the package is
unacceptable. A reported two-phase interleaved buck
converter achieves 64% efficiency for output powers
between 300 mW and 400 mW at 65 MHz switching
frequency, but a 0.18-μm SiGe process was used with an
additional top copper metallization. This is unpractical for
the integration with nm-CMOS circuits [7]. Similarly, a
single-stage buck converter realized by adding additional
process steps to a standard CMOS process to implement a
MEMS-based inductor achieves an efficiency below 60%
at 10 MHz and 75 mW output power [8].
This paper aims at demonstrating the feasibility of flip-
chipping a standard-CMOS active die on top of a silicon-
based passive-integration die for realizing an integrated
DC-DC down converter. Since processing the passive die
involves significantly fewer masks than processing a nm-
CMOS active die, placing the relatively area-consuming
passive components on a separate die makes sense from a
low-cost point-of-view. The realized SiP aims at output
powers in the 100-mW range and fits inside a standard
QFP64 package.
Section II highlights the main design aspects of the
integrated converter, including design of the active die and
determination of the needed passive-component values.
Section III gives more details on the used passive-
integration process and the design of the passive die,
particularly on the design of the LC output filter, and the
complete SiP. The main measurement results are
summarized in section IV. Finally, conclusions are drawn
in section V.
II. D
ESIGN
A
SPECTSOFTHE
I
NTEGRATED
DC-DC
D
OWN
C
ONVERTER
As described in section I, the use of a low-inductance
integrated inductor necessitates a high switching
frequency, which leads to increased switching losses
without proper measures. Therefore, capacitive switching
losses should be minimized using ZVS measures. In a
buck converter with synchronous rectification, as
considered in this paper, ZVS can be achieved by proper
control of the power switches and by allowing the
inductor current to go negative. This is explained with
reference to the general block diagram of a synchronous
buck converter with corresponding waveforms as shown
in Fig. 1.
When the PMOST is on (inverse of V
G,P
equal to V
in
in
Fig. 1), the inductor current I
L
ramps up linearly. At the
moment the PMOST switches off, the positive inductor
current discharges the parasitic switch capacitance C
x
at
the switching LX node between the two power MOSTs.
With proper control of the dead time between switching
off the PMOST and switching on the NMOST, the
NMOST can be switched on when the drain-source
voltage is zero. The capacitive losses are now reduced,
since C
x
has been discharged by the inductor current I
L
.
When the NMOST is on (V
G,N
equal to V
in
), current I
L
ramps down linearly. When the current ripple ΔI is large
enough, current through the NMOST will reverse and I
L
will go negative. At the moment the NMOST switches off,
I
L
will now charge C
x
. With proper dead-time control the
PMOST can now be switched on when the drain-source
voltage is zero, again reducing capacitive losses. Note that
the transition times at the LX node depend on I
L
and
therefore on the load current. Therefore, in order to
prevent that the MOSTs are switched on too early, leading
to remaining capacitive switching losses, or too late,
leading to parasitic body-diode losses, the dead-time
control needs to be adaptive for optimum efficiency.
Various examples of adaptive dead-time control to
reduce capacitive switching losses in high-switching-
frequency synchronous DC-DC down converters can be
found in literature [9],[10],[11]. The ZVS DC-DC down
converter in [9] with an input voltage V
in
of 40 V applies a
constant-off-time controller, where the frequency is varied
to modulate the duty cycle. This leads to a constant value
of the current ripple ΔI large enough to ensure inductor-
current reversal, since it is proportional to V
out
T
off
. A
Delay-Locked-Loop (DLL) is used to ensure that the
drain-source voltage V
ds
crossing zero and the gate-source
voltage V
gs
passing the threshold voltage V
t
occur at the
same moment. The ZVS DC-DC down converter
described in [10],[11] with V
in
=2 V is used for Voltage-
Regulator Module (VRM) applications. An additional
capacitor is added in parallel to C
x
to increase the high-
low and low-high transition times at the LX node. This
enables more precise adaptive dead-time control, since
delays in e.g. comparators in the control loop and gate
drivers become less influential. As in [9], V
ds
zero-
crossing and V
gs
V
t
-crossing comparators are used, the
outputs of which are fed to an analog DLL.
The integrated DC-DC down converter described in this
paper has a relatively low input voltage of 1.8 V.
Moreover, its output power is relatively low, leading to
relatively small power switches and therefore relatively
small parasitic LX-node capacitance C
x
. The losses
f
s
C
x
V
in
2
at a switching frequency f
s
of e.g. 50 MHz are
3337
(a) (b)
Figure 3. (a) Schematic representation of the trench-MOS
capacitor, (b) Cross-sectional SEM image of a complete trench-MOS
capacitor structure in dry-etched silicon [13]
DT
(1-D)T
Active die
Passive die
V
in
C
out
L
C
in
GND
Duty-
cycle
control
Frequency
control
Dela
y
control
PWM
OR
LX
1
2
3
4
5
6
I
L
0
DT (1-D)T
EN
EN
Figure 2. Block diagram of the integrated inductive DC-
DC down
converter
therefore in the same order as the power consumption of
the adaptive dead-time controller reported in [11]. We
therefore chose to implement a simpler ZVS scheme that
may not be perfect, but also hardly consumes any
additional power.
A block diagram of the implemented DC-DC down
converter including the main components on the active
and passive die is shown in Fig. 2. The active die contains
the power stage, consisting of a PMOST and NMOST
with corresponding drivers 1 and 2, digital circuitry to
implement a simple form of ZVS for the reduction of
capacitive switching losses and a Pulse-Width Modulation
(PWM) generator. No closed-loop control has been
implemented yet, because we chose to focus on the
technological aspects of the construction of a two-die SiP
DC-DC converter, keeping the active-die design as simple
as possible. This implies that the desired V
out
is obtained
by setting the correct duty cycle D via a 6-bit digital input
code externally. The frequency of the PWM generator is
controlled externally as well. The passive die includes the
decoupling capacitor C
in
, inductor L and output capacitor
C
out
.
The ZVS operation of the power stage is achieved by
monitoring the voltage at the LX node, see Fig. 2. First,
consider switching off the PMOST at the end of the period
DT. As soon as the PMOST has been switched off, the
coil current I
L
will discharge the LX node, leading to a
rapid decrease in voltage. Buffer 3 will pass this falling
edge on to the input of inverter 5, which is enabled by the
PWM signal going ‘high’ at the start of period (1-D)T. As
a result, the logic ‘high’ signal is passed on to driver 2,
switching on the NMOST. The NMOST is switched off at
the end of period (1-D)T by disabling inverter 5. When
coil current I
L
is negative (into the LX node), the LX-node
voltage will increase. This is again detected by buffer 3,
which passes the rising edge on to the input of inverter 4
via an OR port. Inverter 4 is enabled by the PWM signal
going ‘low’ at the start of period DT. Now, the logic ‘low’
signal is passed on to driver 1, switching on the PMOST.
For high load currents, I
L
will no longer become negative.
Therefore, an alternative path is needed to turn on the
PMOST. When the gate of the NMOST goes ‘low’, the
output of inverter 6 goes ‘high’ after a programmable
delay. This signal is passed on in parallel to the LX-node
signal path and will enforce the PMOST to switch on,
even if the LX voltage is still low. This prevents a dead-
lock situation, but should be avoided in nominal cases.
Sizing of the MOSTs in the power stage has been
optimized by minimizing combined switching and
resistive losses for a switching frequency of 50 MHz, an
output current of 100 mA, and an inductance value of 20
nH. The PMOST was sized roughly a factor 3 larger than
the NMOST to compensate for the mobility difference of
holes and electrons. Based on the sizes of the power
MOSTs, the driver circuits have been optimized for
optimum efficiency [12]. The PMOST driver uses 4 stages
and a tapering factor of 3.3, whereas the NMOST driver
uses two stages and a tapering factor of 4.5. The active die
was realized in standard 5-metal-layer 0.18-μm CMOS.
The chosen inductance value is a trade-off between
occupied area and total efficiency. Given the inductance
value of 20 nH, the output capacitor value was chosen to
be 75 nF to obtain a maximum peak-to-peak voltage ripple
at 50% duty cycle of 15 mV, excluding the influence of
equivalent series inductance (ESL) and resistance (ESR)
of the output capacitor. More information on the design of
the LC output filter will be given in the next section. Since
the switching frequency is relatively high, proper
decoupling of the power stage is critical and particularly
the series inductance in the connections of C
in
should be
very low. As will be described in the next section, the
value of the decoupling capacitance was chosen as large
as possible.
III. P
ASSIVE
-
INTEGRATION
P
ROCESS
,P
ASSIVE
-D
IE
D
ESIGN AND
S
I
P
C
ONSTRUCTION
The proprietary Passive-Integration Connective
Substrate (PICS
TM
) process is silicon-based and provides a
platform for the integration of resistors, capacitors and
inductors [13],[14],[15]. It offers interesting advantages
for realizing integrated DC-DC converters. First, it
achieves large capacitance densities by utilizing trench-
MOS capacitors. The PICS version used in this work
achieves a density of 80 nF/mm
2
[15]. Secondly, an 8-μm
thick copper top-metal layer available in this PICS version
in addition to the first aluminum metal layer enables the
design of spiral air-core inductors with reasonable
performance. Fig. 3 illustrates the trench-MOS capacitor
used to realize C
in
and C
out
as well a cross-sectional SEM
image of the capacitor structure.
In order to form the high-density capacitors, pores of
roughly 1 μm width and 30 μm depth are dry-etched in a
high-resistivity (1-5 kΩcm) silicon substrate. The bottom
electrode of the MOS capacitor structure in Fig. 3 is
formed by making the pore walls of the structure highly
conductive (n
+
-doped bottom electrode). The dielectric is
formed by an ONO (Oxide-Nitride-Oxide) layer. The
thickness of 30 nm shown in Fig. 3b corresponds to a
capacitance density of 30 nF/mm
2
. The top electrode is
formed by filling the pores with n-type in-situ-doped poly
silicon. The top and bottom electrodes are then contacted
with first-metal-layer aluminum. The achieved breakdown
voltage at 80 nF/mm
2
capacitance density is 15.5 V, which
3338
Figure 4. Photograph of the realized 20-nH planar air-core
inductor in a separately laid-out version for wafer-level testing without
the capacitor in the middle
Figure 5. Photograph of the passive-die design
(a) (b)
Figure 6. (a) CMOS die flip-chipped on PICS wafer before dicing,
(b) CMOS/PICS sandwich placed in QFP64 package
is sufficient for use in the low-voltage DC-DC converters
as considered in this paper.
In a space-saving layout, the output capacitor C
out
has
been realized inside the 20-nH inductor. Since the output
capacitance needed to be 75 nF, C
out
occupied a surface
area of 1.3 x 1.3 mm
2
to allow for some overhead for
routing the connections to the capacitor electrodes. Since
a square planar inductor type was chosen for simplicity of
design, this implied that the inner dimension of the
inductor needed to be 1.3 mm x 1.3 mm as a boundary
condition. A basic mathematical model for planar air coils
was used to calculate first-order inductor dimensions that
were later optimized using electro-magnetic Momentum
TM
simulations. This led to an inductor design with 3 turns
with 80-μm wide copper tracks spaced 8 μm apart, i.e. the
minimum possible distance between two copper tracks.
This led to a total area of the LC filter of 1.8 mm x 1.8
mm. The track width of the inductor was chosen as a
compromise between parasitic series resistance and area,
where the latter was restricted by the available package.
The parasitic series resistance is also highly influenced by
the length of the aluminum underpass used to contact the
inner part of the winding. Moreover, the total area
between the copper tracks forming the inductor and the
aluminum underpass also determines the resonance
frequency of the inductor, which should be significantly
higher than the switching frequency. This also led to an
optimization constraint, where the resonance frequency
was chosen to be roughly 1 GHz. A photograph of a
realized 20-nH planar air-core inductor without the
capacitor in the middle is shown in Fig. 4. The differential
Ground-Signal-Ground (GSG) probe pads for wafer
testing of this inductor are shown top left. The position of
the underpass has been indicated as well.
Very thin metal fingers have been used to alternately
connect to the top and bottom electrodes of C
out
to reduce
eddy-current losses. This also led to splitting the capacitor
up in many small-valued parallel capacitors. The copper
top metal layer was used for routing for further reduction
of the ESR and ESL of the capacitor. Since the bottom
electrode of the capacitor had to be connected to the
ground node of the DC-DC converter, the connection to
this electrode also had to be routed to the outside of the
inductor using an underpass. Various thin aluminum
tracks were used in parallel here. The optimization
criterion in this case was to balance the ESR of the
capacitor, which increases with smaller track widths
and/or less tracks in parallel, with the inductor resonance
frequency that decreases with larger tracks widths and/or
more tracks in parallel. Finally, capacitor C
in
was
designed in a similar way as C
out
, using many small
capacitors in parallel. Filling the complete available space
underneath the active die with this capacitor maximized
its value to roughly 300 nF. A photograph of the passive-
die design is shown in Fig. 5. The bumping area for flip-
chipping the active die is shown at the bottom, including
decoupling capacitor C
in
. The LC filter with output
capacitor C
out
in the middle can be partly seen at the top of
Fig. 5.
The complete SiP was formed by flip-chipping the
0.18-μm CMOS active die facedown on the passive die
using gold stud bumps and thermo compression. To
reduce the impedance between the power-stage supply and
ground connections on the active die and the decoupling
capacitor and LC filter on the passive die three bumps
were used in parallel for both the V
in
and GND
connections. After placing the active dies on the passive
wafer, the passive wafer was diced and the resulting
sandwiches of active-die-on-passive-die were bonded in
standard QFP64 packages. Photographs of the flipped
active die on top of the passive wafer before dicing and
the diced CMOS/PICS sandwich inside the QFP64
package are shown in Fig. 6.
IV. M
EASUREMENT
R
ESULTS
The LC filter has also been laid out separately
elsewhere on the PICS wafer to investigate the impact of
placing C
out
inside the inductor. GSG probe pads and
proper de-embedding structures were added to allow
proper on-wafer characterization of the structures. The full
impact of placing the capacitor in the middle of the
inductor could not be predicted during design, since
electro-magnetic simulation of the complete 3D capacitor
structure was not possible with Momentum
TM
. Only the
impact of the thin metal connections to the capacitor could
be taken into account. Fig. 7 shows the measured
Underpass
C
in
LC filter
