Approximate matrix inversion for high-throughput data detection in the large-scale MIMO uplink

TLDR: This paper proposes a novel VLSI architecture to efficiently compute the approximate inverse using a systolic array and shows reference FPGA implementation results for various system configurations.

Abstract: The high processing complexity of data detection in the large-scale multiple-input multiple-output (MIMO) uplink necessitates high-throughput VLSI implementations In this paper, we propose - to the best of our knowledge - first matrix inversion implementation suitable for data detection in systems having hundreds of antennas at the base station (BS) The underlying idea is to carry out an approximate matrix inversion using a small number of Neumann-series terms, which allows one to achieve near-optimal performance at low complexity We propose a novel VLSI architecture to efficiently compute the approximate inverse using a systolic array and show reference FPGA implementation results for various system configurations For a system where 128 BS antennas receive data from 8 single-antenna users, a single instance of our design processes 19M matrices/s on a Xilinx Virtex-7 FPGA, while using only 39% of the available slices and 36% of the available DSP48 units