Open Access
Architecture of FPGAs and CPLDs: A Tutorial
TLDR
This paper provides a tutorial survey of architectures of commercially available high-capacity field-programmable devices (FPDs) and gives examples of applications of each type of device.Abstract:
This paper provides a tutorial survey of architectures of commercially available high-capacity field-programmable devices (FPDs). We first define the relevant terminology in the field and then describe the recent evolution of FPDs. The three main categories of FPDs are delineated: Simple PLDs (SPLDs), Complex PLDs (CPLDs) and Field-Programmable Gate Arrays (FPGAs). We then give details of the architectures of all of the most important commercially available chips, and give examples of applications of each type of device.read more
Citations
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Journal ArticleDOI
MorphoSys: an integrated reconfigurable system for data-parallel and computation-intensive applications
TL;DR: The MorphoSys architecture is described, including the reconfigurable processor array, the control processor, and data and configuration memories, and the suitability of MorphoSy for the target application domain is illustrated with examples such as video compression, data encryption and target recognition.
Journal ArticleDOI
Design and Implementation of the MorphoSys Reconfigurable ComputingProcessor
Ming-Hau Lee,H. Singh,Guangming Lu,Nader Bagherzadeh,Fadi J. Kurdahi,Eliseu M. Chaves Filho,Vladimir Alves +6 more
TL;DR: The results indicate that the MorphoSys system can achieve significantly better performance for most of these applications in comparison with other systems and processors.
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Measurement and Instrumentation Principles
TL;DR: In this paper, the authors present a survey of the state-of-the-art literature in the area of measurement and instrumentation, with a focus on the use of intelligent and distributed instrumentation.
Journal ArticleDOI
Reconfigurable instruction set processors from a hardware/software perspective
TL;DR: This paper presents the design alternatives for reconfigurable instruction set processors (RISP) from a hardware/software point of view.
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A FPGA based implementation of Sobel edge detection
TL;DR: An architecture for Sobel edge detection on Field Programmable Gate Array (FPGA) board, which is inexpensive in terms of computation and reduces the time and space complexity compare to two existing architectures.
References
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Journal ArticleDOI
Architecture of field-programmable gate arrays
TL;DR: A survey of field-programmable gate array (FPGA) architectures and the programming technologies used to customize them is presented and a classification of logic blocks based on their granularity is proposed, and several logic blocks used in commercially available FPGAs are described.
BookDOI
Field-Programmable Gate Array Technology
TL;DR: The purpose of this chapter was to discuss the design and implementation of SRAM Programmable FPGAs, as well as some of the techniques used in the development of Erasable Programmable Logic Devices.
Journal ArticleDOI
Field-programmable gate arrays
TL;DR: FPGAs enable engineers to mitigate the effects entailed by the wellknown tradeoff in computing between cost and performance, and combine the advantages of both general-purpose processors and specialized circuits.
Proceedings ArticleDOI
Dielectric based antifuse for logic and memory ICs
Esmat Z. Hamdy,John L. McCollum,S.-O. Chen,Steve S. Chiang,S. Eltoukhy,J. Chang,T. Speers,Amr M. Mohsen +7 more
TL;DR: The authors describe a programmable low-impedance circuit element (PLICE), which is a dielectric-based antifuse for use in both logic and memory ICs and the reliability of both the programmed and unprogrammed states is demonstrated to be better than 40 years.
Journal ArticleDOI
A very-high-speed field-programmable gate array using metal-to-metal antifuse programmable elements
TL;DR: In this paper, the authors describe the logic cell structure, interconnect architecture, performance characteristics and CAE tools developed for the QL8 × 12, the first member of a family of high-speed FPGAs.