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Journal ArticleDOI

Automatic Single Event Effects Sensitivity Analysis of a 13-Bit Successive Approximation ADC

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TLDR
Analog Fault Tolerant University of Seville Debugging System (AFTU) is presented, a tool to evaluate the Single-Event Effect (SEE) sensitivity of analog/mixed signal microelectronic circuits at transistor level.
Abstract
This paper presents Analog Fault Tolerant University of Seville Debugging System (AFTU), a tool to evaluate the Single-Event Effect (SEE) sensitivity of analog/mixed signal microelectronic circuits at transistor level. As analog cells can behave in an unpredictable way when critical areas interact with the particle hitting, there is a need for designers to have a software tool that allows an automatic and exhaustive analysis of Single-Event Effects influence. AFTU takes the test-bench SPECTRE design, emulates radiation conditions and automatically evaluates vulnerabilities using user-defined heuristics. To illustrate the utility of the tool, the SEE sensitivity of a 13-bits Successive Approximation Analog-to-Digital Converter (ADC) has been analysed. This circuit was selected not only because it was designed for space applications, but also due to the fact that a manual SEE sensitivity analysis would be too time-consuming. After a user-defined test campaign, it was detected that some voltage transients were propagated to a node where a parasitic diode was activated, affecting the offset cancelation, and therefore the whole resolution of the ADC. A simple modification of the scheme solved the problem, as it was verified with another automatic SEE sensitivity analysis.

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Citations
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Journal ArticleDOI

An overview of radiation effects on electronic devices under severe accident conditions in NPPs, rad-hardened design techniques and simulation tools

TL;DR: A high-level overview in an organized fashion of radiation effects on electronics; design techniques to minimize such effects; and modeling and simulation tools available is provided to provide a comprehensive coverage on this subject.
Journal ArticleDOI

Design of a Radiation Hardened Power-ON-Reset

TL;DR: In this article, a power-on-reset intellectual property (IP) block for the RD53 collaboration, a radiation hardening by design circuit to withstand the High-Luminosity Large Hadron Collider tracker radiation environment, is presented.
Journal ArticleDOI

A BICS-based strategy for mitigating the effects of single event transients on SAR converter

TL;DR: A new strategy to mitigate the effects of single event transients (SETs) on the analog part of the Successive Approximation Register (SAR) Analog-To-Digital Converter (ADC) and can be combined with conventional radiation-hardened methods to achieve higher reliability.
Journal ArticleDOI

Pulse Quenching and Charge-Sharing Effects on Heavy-Ion Microbeam Induced ASET in a Full-Custom CMOS OpAmp

TL;DR: In this article, charge sharing effects on analog single-event transients are experimentally observed in a fully custom designed, 180-nm complementary metal-oxide-semiconductor (CMOS) operational amplifier by means of a heavy-ion microbeam.
Journal ArticleDOI

Analog CMOS Readout Channel for Time and Amplitude Measurements With Radiation Sensitivity Analysis for Gain-Boosting Amplifiers

TL;DR: In this paper, the authors proposed a method to select the value of the QFG capacitors, minimizing the area occupancy while maintaining robustness to radiation, and implemented a readout system using compact gain boosting techniques based on quasi-floating gate transistors achieving accurate energy measurement with good resolution.
References
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Journal ArticleDOI

Collection of Charge on Junction Nodes from Ion Tracks

TL;DR: In this paper, an approximate analytical solution expressed as I(t) = Io [exp(-?t) - exp (-st)] (1) where Io is approximately the maximum current, 1/? is the collection time constant of the junction, and 1/s is the time constant for initially establishing the ion track.
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Design techniques for high-speed, high-resolution comparators

TL;DR: In this article, precision techniques for the design of comparators used in high-performance analog-to-digital converters employing parallel conversion stages are described, and circuit designs achieving 12-b resolution in both BiCMOS and CMOS 5-V technologies are presented.
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An Ultra Low Energy 12-bit Rate-Resolution Scalable SAR ADC for Wireless Sensor Nodes

TL;DR: A resolution-rate scalable ADC for micro-sensor networks is described, based on the successive approximation register (SAR) architecture, which has two resolution modes: 12 bit and 8 bit, and its sampling rate is scalable, at a constant figure-of-merit, from 0-100 kS/s and 0-200 kS /s, respectively.
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Gate sizing to radiation harden combinational logic

TL;DR: A gate-level radiation hardening technique for cost-effective reduction of the soft error failure rate in combinational logic circuits is described, which uses a novel gate (transistor) sizing technique that is both efficient and accurate.
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Monte Carlo Simulation of Single Event Effects

TL;DR: In this paper, a Monte Carlo approach for estimating the frequency and character of single event effects based on a combination of physical modeling of discrete radiation events, device simulations to estimate charge transport and collection, and circuit simulations to determine the effect of the collected charge.