Open Access
Brick and mortar chip fabrication
Mark Oskin,Martha A. Kim +1 more
TLDR
Brick and mortar chips are introduced, which aim to obtain the benefits of Moore's Law without the financial side effects, and software partitioning and mapping techniques which balance communication costs against computational resource contention are developed.Abstract:
While Moore's Law has advanced the semiconductor and technology industries, it has simultaneously driven up the cost of engineering a chip in a modern silicon process. The result is that fewer and fewer chips are produced in larger and larger volumes, stifling hardware diversity.
This thesis introduces brick and mortar chips, which aim to obtain the benefits of Moore's Law without the financial side effects. Brick and mortar chips are made from small, pre-fabricated hardware components (called bricks) that are bonded in a designer-specified arrangement to a communication backbone chip which serves as the mortar (called the I/O cap).
Our research examines several aspects of this chip manufacturing system. We develop a family of functional bricks, demonstrating a methodology for developing families that make efficient use of physical computation and communication resources. For high-performance communication between arbitrary combinations of bricks we propose a polymorphic on-chip network. This network allows a single I/O cap to be configured to implement the ideal network for any particular application. We analyze a low-cost, physical component assembly technique called fluidic self-assembly, and find that the chip production rate is intertwined with the architectural design of the components. To minimize application execution time on these partitioned chips, we develop software partitioning and mapping techniques which balance communication costs against computational resource contention.
We close with a case study: an analysis of a brick and mortar implementation of a chip multiprocessor. Despite this being a highly latency sensitive design, our measurements indicate a worst case 36% average slowdown in application execution compared to a traditional, monolithic chip. Based on this, our cost analysis, and a survey of related technologies, we conclude that brick and mortar offers the best available performance for its price.read more
Citations
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1.27Gb/s/pin 3mW/pin wireless superconnect (WSC) interface scheme
Kouichi Kanda,Danardono Dwi Antono,Koichi Ishida,Hiroshi Kawaguchi,Tadahiro Kuroda,Takayasu Sakurai +5 more
TL;DR: In this article, a low power high speed chip-to-chip interface scheme is described having a density of 625pins/mm/sup 2/. The interface utilizes capacitively coupled contactless minipads, returnto-half-V/sub 00/ signaling and sense amplifying F/F.
Proceedings ArticleDOI
Panel - Structured/platform ASIC apprentices Which platform will survive your board room?
R. Wilson,J. Gianelli,Christopher L. Hamlin,Steve Leibson,R. Tobias,K. McElvain,I. Bolsens,Raul Camposano +7 more
TL;DR: This lively panel will discuss whether it is FPGAs, structured/platform ASICs, or something else that stand to gain the most ground from the projected $25B ASIC market, and why.
References
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The SPLASH-2 programs: characterization and methodological considerations
TL;DR: This paper quantitatively characterize the SPLASH-2 programs in terms of fundamental properties and architectural interactions that are important to understand them well, including the computational load balance, communication to computation ratio and traffic needs, important working set sizes, and issues related to spatial locality.
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William J. Dally,Brian Towles +1 more
TL;DR: This book offers a detailed and comprehensive presentation of the basic principles of interconnection network design, clearly illustrating them with numerous examples, chapter exercises, and case studies, allowing a designer to see all the steps of the process from abstract design to concrete implementation.
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Solution Properties of Poly(N-isopropylacrylamide)
M. Heskins,J. E. Guillet +1 more
TL;DR: In this paper, a lower critical solution temperature of poly(N-isopropyl acrylamide was found to be due to an entropy effect, which was attributed to the formation of nonpolar and intermolecular hydrogen bonds.
Journal ArticleDOI
Simics: A full system simulation platform
Peter S. Magnusson,M. Christensson,J. Eskilson,D. Forsgren,G. Hallberg,J. Hogberg,Fredrik Larsson,A. Moestedt,Bengt Werner +8 more
TL;DR: Simics is a platform for full system simulation that can run actual firmware and completely unmodified kernel and driver code, and it provides both functional accuracy for running commercial workloads and sufficient timing accuracy to interface to detailed hardware models.
Book
Deadlock-free message routing in multiprocessor interconnection networks
TL;DR: A deadlock-free routing algorithm can be generated for arbitrary interconnection networks using the concept of virtual channels, which is used to develop deadlocked routing algorithms for k-ary n-cubes, for cube-connected cycles, and for shuffle-exchange networks.