Compiler optimization on instruction scheduling for low power
Chingren Lee,Jenq Kuen Lee,TingTing Hwang,Shi-Chun Tsai +3 more
- pp 55-60
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TLDR
It is proved that the greedy algorithm always gives the optimal switching activities of the instruction bus and the problem is NP-hard, and a heuristic algorithm is proposed.Abstract:
In this paper, we investigate the compiler transformation techniques to the problem of scheduling VLIW instructions aimed to reduce the power consumption on the instruction bus. It can be categorized into two types: horizontal and vertical scheduling. For the horizontal case, we propose a bipartite-matching scheme. We prove that our greedy algorithm always gives the optimal switching activities of the instruction bus. In the vertical case, we prove that the problem is NP-hard, and propose a heuristic algorithm. Experimental results show average 13% improvements with 4-way issue architecture and average 20% improvement with 8-way issue architecture for power consumptions of instruction bus as compared with conventional list scheduling for an extensive set of benchmarks.read more
Citations
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System-level power-aware design techniques in real-time systems
Osman Unsal,Israel Koren +1 more
TL;DR: An overview of power-aware techniques for the real-time system engineer as well as an up-to-date reference list for the researcher are provided.
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Reliable software for unreliable hardware: embedded code generation aiming at reliability
TL;DR: A compilation technique for reliability-aware software transformations is presented, which incurs 60%-80% lower application failures, averaged over various fault injection scenarios and fault rates.
Journal ArticleDOI
Compiler optimization on VLIW instruction scheduling for low power
TL;DR: It is proved that the greedy bipartite-matching scheme always gives the optimal switching activities of the instruction bus for given VLIW instruction scheduling policies.
Proceedings ArticleDOI
Power-aware modulo scheduling for high-performance VLIW processors
Han-Saem Yun,Jihong Kim +1 more
TL;DR: Experimental results show that the proposed scheduling technique significantly improves the power characteristics of high-performance processors over an existing power-unaware modulo scheduling technique.
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Clustered loop buffer organization for low energy VLIW embedded processors
TL;DR: A clustered loop buffer organization is proposed, where the loop buffers are partitioned and functional units are logically grouped to form clusters, along with two schemes for buffer control, which regulate the activity in each cluster.
References
More filters
Journal ArticleDOI
Low-power CMOS digital design
TL;DR: In this paper, techniques for low power operation are presented which use the lowest possible supply voltage coupled with architectural, logic style, circuit, and technology optimizations to reduce power consumption in CMOS digital circuits while maintaining computational throughput.
Journal ArticleDOI
Fibonacci heaps and their uses in improved network optimization algorithms
TL;DR: Using F-heaps, a new data structure for implementing heaps that extends the binomial queues proposed by Vuillemin and studied further by Brown, the improved bound for minimum spanning trees is the most striking.
Journal Article
Low-Power CMOS Digital Design
TL;DR: An architecturally based scaling strategy is presented which indicates that the optimum voltage is much lower than that determined by other scaling considerations, and is achieved by trading increased silicon area for reduced power consumption.
Book
Computer Architecture: A Quantitative Approach, 2nd Edition
TL;DR: A quantitative approach to computer architecture a quantitative approach 5th edition computer architecture quantitative approach solution manual computer Architecture quantitative approach solutions manual computer architecture an quantitative approach 3rd editionComputer architecture, fifth edition.
Journal ArticleDOI
Power analysis of embedded software: a first step towards software power minimization
TL;DR: A power analysis technique is developed that has been applied to two commercial microprocessors and can be employed to evaluate the power cost of embedded software and can help in verifying if a design meets its specified power constraints.