Proceedings ArticleDOI
Design and Algorithms for Parallel Testing of Random Access and Content Addressable Memories
Pinaki Mazumder,Janak H. Patel,W.K. Fuchs +2 more
- pp 689-694
TLDR
Based on this design for testability approach, parallel testing algorithms for CAMs and RAMs are developed for a broad class of pattern sensitive faults and the resulting test procedures are significantly more efficient than previous approaches.Abstract:
This paper presents a design strategy for efficient and comprehensive parallel testing of both Random Access Memory (RAM) and Content Addressable Memory (CAM). Based on this design for testability approach, parallel testing algorithms for CAMs and RAMs are developed for a broad class of pattern sensitive faults. The resulting test procedures are significantly more efficient than previous approaches. For example, the design for testability strategy allows an entire w word CAM to be read in just one operation with a resulting speed up in testing as high as w. In the case of an n bit RAM, the improvement in test efficiency is by a factor of O(√n). The overall reduction in testing time is considerable for large size memories.read more
Citations
More filters
Journal ArticleDOI
Integrated circuit testing for quality assurance in manufacturing: history, current status, and future trends
TL;DR: In this article, the authors examine the developments in IC testing from the historic, current status and future view points and relate new test paradigms that have the potential to fundamentally alter the methods used to test mixed-signal and RF parts.
Patent
Semiconductor memory having test circuit and test method thereof
TL;DR: In this paper, a test circuit is used to compare the test data written in the memory cells connected to the selected word line with the expected value data supplied from the external terminal in correspondence with the selected line.
Journal ArticleDOI
VLSI algorithms, architectures, and implementation of a versatile GF(2/sup m/) processor
TL;DR: An extensive model and algorithms for detecting faults in SRAM-based dual-port and uni-port CAMs (Content Addressable Memories) and two new detection algorithms (directly compatible with the world-oriented March C algorithm, as widely used in existing commercial tools) are proposed.
Journal ArticleDOI
Parallel testing for pattern-sensitive faults in semiconductor random-access memories
Pinaki Mazumder,Janak H. Patel +1 more
TL;DR: Although the algorithm is designed to detect pattern-sensitive faults, the modified architecture can be readily used to speed up other conventional algorithms of linear complexity by a factor of O( square root n).
Journal ArticleDOI
Testing content-addressable memories using functional fault models and march-like algorithms
Kun-Jin Lin,Cheng-Wen Wu +1 more
TL;DR: A complete, compact test is proposed, which has low complexity and is suitable for modern high-density and large-capacity CAMs-it requires only 2N+3w+2 compare operations and 8N write operations to cover the functional fault models discussed.
References
More filters
Journal ArticleDOI
Testing Memories for Single-Cell Pattern-Sensitive Faults
TL;DR: It is demonstrated that minimum-length SPSF tests can be inherently asymmetric and interpreted as polyominoes.
Journal ArticleDOI
Test Procedures for a Class of Pattern-Sensitive Faults in Semiconductor Random-Access Memories
TL;DR: A class of pattern-sensitive faults in semiconductor random-access memories are studied and efficient test procedures to detect and locate modeled faults are presented.
Journal ArticleDOI
Detection oF Pattern-Sensitive Faults in Random-Access Memories
TL;DR: Some formal models for pattern-sensitive faults (PSF's) in random-access memories are presented and an efficient procedure for constructing a checking sequence for the memory is presented.
Journal ArticleDOI
A Self-Testing Dynamic RAM Chip
Younggap You,John P. Hayes +1 more
TL;DR: A novel approach to making very large dynamic RAM chips self-testing is presented, based on two main concepts on-chip generation of regular test sequences with very high fault coverage, and concurrent testing of storage-cell arrays to reduce overall testing time.
Proceedings Article
Built-in testing of memory using on-chip compact testing scheme
Kozo Kinoshita,Kewal K. Saluja +1 more
TL;DR: In this article, a new fault model, which encompasses the existing fault models, is proposed and a scheme of testing faults from the new model using built-in testing techniques is proposed.