Design and fabrication of surface trimmed silicon-on-insulator waveguide with adiabatic spot-size converters

TLDR: The proposed surface trimming technique can be potentially used to tune the waveguide cross-section/geometry for phase error correction and/or to avail stronger light-matter interactions at a desired location of an integrated optical circuit.

Abstract: Theoretical and experimental studies reveal that a predefined single-mode rib waveguide fabricated in silicon-on-insulator (SOI) substrate with a device layer thickness of 2 μm can be adiabatically trimmed down to submicron waveguide dimensions (<1  μm), resulting in regional modification of waveguide properties. The fabrication process involves physical trimming/removal of a waveguide surface by plasma etchants that is spatially filtered by a shadow mask with a rectangular aperture inside a reactive ion etching system. The exact position of a shadow mask above a sample surface has been optimized (∼500  μm) to obtain the desired adiabatic spot-size converters of length up to 1 mm at both ends of the trimmed waveguides. For experimental demonstration, three different sets of 15-mm-long single-mode waveguides fabricated in 2-μm SOI were adiabatically trimmed in the middle for three different lengths of 3, 5, and 7 mm, respectively. Excess propagation loss and group index of a trimmed submicron waveguide section were extracted by analyzing the wavelength-dependent Fabry–Perot transmission characteristics of the device with polished input/output end facets. The insertion loss of a typical spot-size converter designed for the guidance of TE-like polarization has been recorded to be ∼0.25  dB for a wide range of wavelengths (1500  nm≤λ≤1600  nm). As predicted by numerical simulation, no polarization rotation has been observed in all the trimmed submicron waveguides. The proposed surface trimming technique can be potentially used to tune the waveguide cross-section/geometry for phase error correction and/or to avail stronger light-matter interactions at a desired location of an integrated optical circuit.