Proceedings ArticleDOI
Design for testability of a 32-bit microprocessor-the TX1
Y. Nozuyama,Akira Nishimura,J. Iwamura +2 more
- pp 172-182
Reads0
Chats0
TLDR
Testable designs of the TX1, a 32-bit microprocessor based on the TRON architecture, are described, resulting in three testable design approaches implemented in an optimized form.Abstract:
Testable designs of the TX1, a 32-bit microprocessor based on the TRON architecture, are described. Clear testing strategies were developed, resulting in three testable design approaches implemented in an optimized form. Logic function test is composed of scan test and self test. Their efficiency is highly enhanced by the use of the bus structure or microinstruction set of the TX1. Fault coverage of over 90% is achieved by them with short testing time (several seconds) and small increase of chip area (4.2%). Design verification is done with scan test and macroblock test. The latter can directly test important manually designed hardware blocks independent of the complicated decode and control logic. The area increase is only 0.4%. It can give useful information for their refinement in the early phase of development. >read more
Citations
More filters
Journal ArticleDOI
A multiple seed linear feedback shift register
Jacob Savir,William H. McAnney +1 more
TL;DR: The authors describe a design of an LFSR (linear feedback shift register) that can easily accommodate a change-of-seeds feature and is controlled by two separate clocks.
Proceedings ArticleDOI
Synthesizing for scan dependence in built-in self-testable designs
L.J. Avra,Edward J. McCluskey +1 more
TL;DR: This paper introduces new design and synthesis techniques that reduce the area and performance overhead of built-in self-test (BIST) architectures such as circular BIST and parallel BIST, and shows that introducing certain types of scan dependence in embedded MISRs can result in reduced overhead and improved fault coverage.
Proceedings ArticleDOI
A multiple seed linear feedback shift register
Jacob Savir,William H. McAnney +1 more
TL;DR: The authors describe the design of an LSSD-(level-sensitive-scan-design) based LFSR (linear feedback shift register) which is capable of changing seeds by applying a pair of clock pulses at the time of the change.
Proceedings ArticleDOI
A test methodology for VLSI chips on silicon
TL;DR: A methodology developed to test high performance VLSI CMOS ICs that have been mounted onto a multichip silicon substrate, covering test from the wafer level, unpopulated substrate, and populated substrate.
Journal ArticleDOI
Design of a 32 bit microprocessor, TX1
TL;DR: A one-phase clock system, which is a better solution for high-speed operation but requires careful design for evading the skew problem, is discussed.
References
More filters
Proceedings Article
Testability features of the MC68020
John R. Kuban,John E. Salick +1 more
TL;DR: A Judicious mixture of the two makes the MC68020 a highly testable chip without significantly affecting die size.
Book ChapterDOI
TRON VLSI CPU: Concepts and Architecture
TL;DR: The TRON VLSI CPU is a high-performance microprocessor for computer applications in the 1990’s that has the following powerful features that do not exist in the conventional architecture of microprocessors.
Book ChapterDOI
TX Series Based on TRONCHIP Architecture
TL;DR: The general development philosophy is described for the TX series which consists of a basic core processor, higher performance ones and superintegrated autonomous derivative processors, which are designed on the single TRONCHIP architecture.
Journal ArticleDOI
Micro/370: a 32-bit single-chip microprocessor
H.H. Chao,Shauchi Ong,M.Y. Tsai,F.W. Shih,J. C. L. Hou,K.W. Lewis,J. Y. F. Tang,C. A. Trempel,R.W. Hadsell,H. N. Yu,P.F. Greier,R.L. Franch,P.E. McCormick,C. V. Davis,A. L. Diamond,T. J. Medve +15 more
TL;DR: In this paper, a 32-bit single-chip microprocessor that directly implements 102 System/370 instructions and supports the emulation of the rest of the instructions is described and the design and verification methodologies and the testing consideration are also described.