Aalborg Universitet
Distributed Secondary Voltage and Frequency Control for Islanded Microgrids with
Uncertain Communication Links
Lu, Xiaoqing; Yu, Xinghuo; Lai, Jingang; Guerrero, Josep M.; Zhou, Hong
Published in:
I E E E Transactions on Industrial Informatics
DOI (link to publication from Publisher):
10.1109/TII.2016.2603844
Publication date:
2017
Document Version
Early version, also known as pre-print
Link to publication from Aalborg University
Citation for published version (APA):
Lu, X., Yu, X., Lai, J., Guerrero, J. M., & Zhou, H. (2017). Distributed Secondary Voltage and Frequency Control
for Islanded Microgrids with Uncertain Communication Links. I E E E Transactions on Industrial Informatics,
13(2), 448 - 460 . https://doi.org/10.1109/TII.2016.2603844
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IEEE TRANSACTIONS ON INDUSTRIAL INFORMATICS, VOL. XX, NO. X, XXX 2016 1
Distributed Secondary Voltage and Frequency
Control for Islanded Microgrids with Uncertain
Communication Links
Xiaoqing Lu, Xinghuo Yu, Fellow, IEEE, Jingang Lai, Josep M. Guerrero, Fellow, IEEE, and Hong Zhou
Abstract—This paper presents a robust distributed secondary
control (DSC) scheme for inverter-based microgrids (MGs) in a
distribution sparse network with uncertain communication links.
By using the iterative learning mechanics, two discrete-time DSC
controllers are designed, which enable all distributed energy
resources (DERs) in a MG to achieve the voltage/frequency
restoration and active power sharing accuracy, respectively. In
special, the secondary control inputs are merely updated at the
end of each round of iteration, and thus each DER only needs
to share information with its neighbors intermittently in a low-
bandwidth communication manner. This way, the communication
costs are greatly reduced, and some sufficient conditions on
the system stability and robustness to the uncertainties are
also derived by using the tools of Lyapunov stability theory,
algebraic graph theory, and matrix inequality theory. The pro-
posed controllers are implemented on local DERs, and thus
no central controller is required. Moreover, the desired control
objective can also be guaranteed even if all DERs are subject to
internal uncertainties and external noises including initial voltage
and/or frequency resetting errors and measurement disturbances,
which then improves the system reliability and robustness. The
effectiveness of the proposed DSC scheme is verified by the
simulation of an islanded MG in MATLAB/SimPowerSystems.
Index Terms—Distributed control, secondary control, discrete-
time, islanded microgrid.
Manuscript received February 1, 2016; revised April 11, 2016, and June
24, 2016; accepted July 21, 2016. This work was supported in part by the
National Natural Science Foundation of China under Grant 61403133, Grant
61532020, and Grant 61573134, in part by the International Postdoctoral
Foundation under Grant 20140034, in part by the Australia Research Council
under Grant 140100544, in part by the China Postdoctoral Innovation Talent
Support Program, in part by the China Postdoctoral Science Foundation under
Grant 2013M540627, in part by the Natural Science Foundation of Hunan
Province under Grant 14JJ3051, and in part by the Doctoral Fund of Ministry
of Education of China under Grant 20130161120016. Paper no. TII-16-0120.
(Corresponding author: Xiaoqing Lu and Jingang Lai.)
X.Q. Lu is with the College of Electrical and Information Engineer-
ing, Hunan University, Changsha 410082, PR China and also with the
School of Engineering, RMIT University, Melbourne VIC 3001, Australia
(e-mail:henanluxiaoqing@163.com).
X. Yu is with the School of Engineering, RMIT University, Melbourne,
VIC 3001, Australia (e-mail:x.yu@rmit.edu.au).
J.G. Lai is with the School of Electrical and Electronic Engineering,
Huazhong University of Science and Technology, Wuhan 430074, PR China
and also with the School of Engineering, RMIT University, Melbourne VIC
3001, Australia (e-mail:laijingang@whu.edu.cn).
J.M. Guerrero is with the Department of Energy Technology, Aalborg
University, 9220 Aalborg, Denmark (e-mail:joz@et.aau.dk).
H. Zhou is with the Department of Automation, Wuhan University, Wuhan
430072, PR China (e-mail: hzhouwuhee@whu.edu.cn).
Color versions of one or more of the figures in this paper are available
online at http://ieeexplore.ieee.org.
Digital Object Identifier XX.XXXX/TII.2016.XXXXXXX
I. INTR ODUCTION
M
ICROGRIDS are able to achieve the effective integra-
tion of large number of DERs via DC/AC inverters [1].
In general, MGs transfer from grid-connected mode to islanded
mode induced by disturbances or faults autonomously. The
local primary control (droop technique) embedded in inverters
preserves the autonomy of each DER [2]. When load changes
occur in islanded MGs, different DERs in the network should
adjust their output powers to keep the dynamical balance
between the loads and DERs across the MG. However, the
inherent defect of droop control is that the deviations of
frequency and voltage amplitude can be significantly impacted
by loads [3]-[5]. Thus, the secondary control is employed to
restore the frequency and voltage to the desired values.
Different from traditional centralized control for MGs with
many deficiencies, including the high costs generated by the
high-bandwidth communication links, difficulty for the future
extension of MGs [6]-[8], the distributed structure provides
a practically feasible and highly computational efficiency
solution. In view of this, some DSC approaches have been
proposed to achieve voltage/frequency restoration [8],[14], re-
active sharing [9],[17], imbalance voltage compensation [13],
etc. Specially, based on the distributed cooperative control
of multi-agent systems [10],[11], a DSC method for voltage
regulation was proposed [8], which relies on the feedback lin-
earization technique with high gains. However, high gain has a
negative impact on the overall stability of MGs. Then, a DSC
for voltage imbalance compensation was investigated in [13],
which guarantees the achievement of voltage regulation in a
finite time. To regulate the power output of a MG dynamics
consisting of a large number of DERs, a pinning-based DSC
scheme was then presented with uncertain communication
topologies [12], which is of benefit to meet the common
requirements of line switches and plug-and-play operation
in MGs. Further, a DSC approach to regulate the voltage,
frequency, and reactive power was proposed [14], where each
local DER is required to communicate with all the other DERs
across the MG, which has almost the same communication
costs as a centralized control approach. Besides, the detailed
stability analysis is neglected. Moreover, to obtain the trade-
off between voltage regulation and accurate reactive power
sharing, the information (voltages and frequencies) communi-
cation among neighboring DERs plays a key ingredient [15].
However, in the above literatures, it is generally assumed that
1551-3203
c
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See http://www.ieee.org/publications standards/publications/rights/index.html for more information.
2 IEEE TRANSACTIONS ON INDUSTRIAL INFORMATICS, VOL. XX, NO. X, XXX 2016
all DERs can access the system parameters accurately, and the
ubiquitous communication disturbances and noises between
DERs are negligible.
Due to the impact of component mismatches, numerical
errors [16], high frequency component of disturbances and
noises, transient power oscillation caused by the flow of large
reactive power currents [17], it is difficult for each DER to
get the accurate information from its neighbors. Moreover,
those impacts on the stability of low-voltage MGs are more
severe than that of high-voltage ones [17]-[18]. Besides, it
has been recognized that the perturbations existed in the
information exchanges among DERs are usually unavoidable
[13],[19],[20], which inspires us to take the impacts of com-
munication disturbances and noises on the system stability into
account when we design DSC schemes for MGs.
This paper aims to propose a novel DSC scheme for
islanded MGs, which is robust to the interval uncertainties
within information exchanges among all DERs. In detail,
two DSC controllers with discrete-time control inputs for the
achievement of the voltage/frequency restoration and the active
power sharing accuracy will be designed and implemented
on local DERs. With the proposed DSC scheme, each DER
only needs to access partial or limited knowledge of the
system parameters, perform merely local measurements, and
then communicate with its neighbors intermittently. Stability
analysis for the controlled system is also given. Moreover, the
information exchanges among DERs are in the discrete form
and thus greatly reduce the communication costs, which then
makes our results essentially different from the existing meth-
ods that with the continuous-time communications [8],[12].
The rest of this paper is organized as follows. The system
model is formulated in Sec. II, and the proposed DSC scheme
containing two DSC algorithms with discrete-time control in-
puts is designed and analyzed in Sec. III. Then, the numerical
results are simulated via an islanded MG in Sec. IV before
we conclude the work in Sec. V. Finally, an important lemma
of the main results is given in Appendix.
Some necessary notifications are given below. Let ⊗ be the
Kronecker product. For any vectors x, y ∈ R
n
, denote x⊙y =
(x
1
y
1
, · · · , x
n
y
n
)
T
∈ R
n
.
II. PR OBLEM FORMULATION AND PRELIMINARIES
A. Problem Formulation
Consider an inverter-based MG consisting of N DERs. For
the ith DER, the basic internal multiple control loops as well
as the primary and secondary control procedure can be drawn
in Fig. 1. The common d-q reference frame transformation is
used, where d-axis and q-axis for each DER are rotating with
the common reference frequency [8].
As seen in Fig. 1, the current, voltage, and power control
loops are employed in each DER. The primary control proce-
dure is implemented during the power control loop with the
nominal set points V
nom
i
and ω
nom
i
. With the reference values,
V
od
iref
and V
oq
iref
, provided by the power loop, the voltage loop
generates the current reference, i
Ld
iref
and i
Lq
iref
, for the current
loop. Then, the current errors are calculated and finally used
to regulate the outputs of the inverter by SPWM mode.
PI Voltage
Controlle
r
PI Current
Controller
SPWM
Power
Controller
Inverter
Output
Inductor
LC Filter
MG
BUS
Primary
Control
DES
DES
V
w
nom
i
V
o
i
V
o
i
i
o
i
L
Distributed
Secondary
Contro
l
Communication
Network
i
1i +
N
1
nom
i
w
1i -
1 1i i i
w w w
+ -
ˈˈ
o o o
1 1i i i
V V V
+ -
ˈˈ
,
ref
ref
oq
od
i
i
V V
,
ref
ref
q
d
L
L
i
i
i i
abc/dq
abc/dq
abc/dq
abc/dq
,
q
d
L
L
i
i
i i
,
oq
od
i
i
V V
,
oq
od
i
i
i i
0
Virtual
leader
DC
i
V
L
i
i
f
i
L
f
i
C
i
C
Fig. 1. Distributed control for MGs, the red dotted lines represent a sparse
communication network for system information exchanges among DERs.
To compensate the voltage and frequency deviations caused
by the primary control procedure, the secondary control pro-
cedure is applied to generate different nominal set points
for different DERs in a distributed way. In detail, we will
design a DSC scheme by the information exchanges among
the neighboring DERs to update V
nom
i
and ω
nom
i
in each pri-
mary control process, and further restore the terminal outputs,
voltage V
i
and frequency ω
i
, to their desired values, V
DES
and
ω
DES
provided by a virtual leader DER
0
(can be controlled
by the main grid in a connected mode or obtained by the
command DER in a stand-alone mode).
Since an LCL filter is added in each DER so that the output
impedance is highly inductive and dominate any resistive
effects, the following primary control principle is used as the
power control loop [4,14]:
V
i
= V
nom
i
− K
Q
i
Q
i
,
ω
i
= ω
nom
i
− K
P
i
P
i
,
(1)
where V
i
and ω
i
are respectively the actual voltage magnitude
and frequency, Q
i
and P
i
are the measured reactive and
active powers after low-pass filters, and K
Q
i
and K
P
i
are the
associated droop coefficients, respectively.
i i
i i
V i V i
+
oq oq
od od
c
c
i
i
s
w
w
+
i i
i i
V i V i
oq oq
od od
-
c
c
i
i
s
w
w
+
od
i
V
oq
i
V
i
i
od
i
i
oq
abc
/dq
o
i
V
i
i
o
ref
od
i
V
ref
oq
i
V
0
i
w
nom P
i i i
K P
w
-
Q
nom
i i
i
V K Q
-
nom
i
w
nom
i
V
m
i
P
m
i
Q
i
P
i
Q
Fig. 2. Block diagram of the primary control in a power loop.
Here we choose the output voltage magnitude reference
is aligned to the d-axis of reference frame of the ith DER.
Rewrite the droop control principle (1) for the ith DER as
V
od
i
= V
nom
i
− K
Q
i
Q
i
,
V
oq
i
= 0,
ω
i
= ω
nom
i
− K
P
i
P
i
.
(2)
The block diagram of the primary control principle is
shown in Fig.2, where ω
c
i
is the cut-off frequency of the
LU et al.: DISTRIBUTED SECONDARY VOLTAGE AND FREQUENCY CONTROL FOR ISLANDED MICROGRIDS WITH UCL 3
low-pass filters installed in the power control loop, P
m
i
and
Q
m
i
are the instantaneous active and reactive power compo-
nents calculated from the measured output voltage and output
current [19]. Since the output voltage amplitude of the ith
DER is V
i
=
(V
od
i
)
2
+ (V
oq
i
)
2
, the restoration of voltage
amplitude, V
i
→ V
DES
, is achieved by choosing V
nom
i
such
that V
od
i
→ V
DES
by equation (2). The secondary frequency
control is to select ω
nom
i
such that ω
i
→ ω
DES
.
B. Communication Network
For better describing the communication network structure
of a MG, the algebraic digraph theory is adopted here. The
communication network of a MG consisting of N DERs
(labeled 1 through N) is mapped to a digraph G(V, E, A),
where the node set V = {v
1
, v
2
, · · · , v
N
} represents all DERs
and the set of edges E ⊆ V × V represents the communication
links for information exchange. A = (a
ij
)
N×N
is a weighted
adjacency matrix with elements a
ii
= 0 and a
ij
≥ 0. a
ij
> 0
if and only if the edge (v
i
, v
j
) ∈ E. The set of neighbors of
the ith DER v
i
is given by N
i
= {v
j
∈ V : (v
i
, v
j
) ∈ E}.
The Laplacian matrix L = (ℓ
ij
)
N×N
is defined as ℓ
ij
= −a
ij
,
i = j, and ℓ
ii
=
N
j=1
a
ij
for i = 1, · · · , N, which satisfies
L1
N
= 0 with 1
N
= (1, · · · , 1)
T
∈ R
N
.
In addition, the digraph
ˆ
G(A) is used to describe the
interconnection topology of a MG consisting of one virtual
leader-DER, denoted by 0, which cannot receive information
from all other DERs, and N follower-DERs, denoted by
1, · · · , N [25]. Diagonal matrix B = diag{a
10
, · · · , a
N0
} is
called the leader adjacency matrix, where a
i0
> 0 if follower-
DER
i
is connected to DER
0
across the communication link
(v
0
, v
i
), otherwise a
i0
= 0.
For the uncertain communication links, we assume that each
nonzero weight a
ij
satisfies 0 < a
ij
≤ a
ij
≤ a
ij
with the
nonnegative bounds a
ij
and a
ij
, which respectively correspond
to the lower bound matrix A and the upper bound matrix
A. Denote the digraph associated with adjacency matrices A
and A by G(A) and G(A), respectively. Obviously, G(A) is
a spanning subgraph of G(A), and both G( A) and G(A) are
spanning subgraphs of G(A), and their associated neighbor
sets of DER
i
satisfy N
i
⊆ N
i
⊆ N
i
.
The voltage and frequency may possess different network
structures and weights. To derive the connectivity requirements
for each variable, this paper relates to three digraphs,
ˆ
G(A
V
),
ˆ
G(A
ω
), and G(A
P
), corresponding to the networks of fre-
quency, voltage, and active power, respectively.
III. DSC SCHEME WITH DISCRETE CONTROL INPUTS
In practice, the DSC scheme can be implemented by the
communication equipment and network, by which the con-
tinuous variables V
od
i
, ω
i
, Q
i
and P
i
are discretized. Thus,
different from the traditional secondary control approaches
with continuous-time control dynamics [8],[12], this section
will present a new DSC scheme with discrete-time control
inputs to achieve the voltage and frequency restoration and
the power sharing accuracy, respectively.
We firstly transform system (2) into a discrete-time system
with sampling period T
s
. Time is discretized into an finite time
0
( )
kk
tt =
0
1
1
( )
k
k
t
t
++
=
1
k
t
T
k
t
*
The th
information exchange
and input update
( 1)k -
*
1
T
k
t
-
0
( )
0
k
( )
( )
( )
( )
( )
( )
1
( )
k
t
+
( )
( )
The th
information exchange
and input update
k
k
t
1
1
+
Sampling period
of the DSC
control modul
e
k k
k st t T T
1
The th round iteration Toltal time: *( )
+
- = ×
k
t
+1
k
t
+1
sT
tD
tD
Fig. 3. Time diagram of the proposed DSC strategy.
sequence of nonempty and bounded intervals, [t
k
, t
k+1
) with
t
0
= 0 and k = 0, 1, 2, · · ·, representing the kth round iteration
index, as shown in Fig. 3. During each interval [t
k
, t
k+1
),
there is a sequence of nonoverlapping subintervals [t
0
k
, t
1
k
),
[t
1
k
, t
2
k
), · · ·, [t
T
∗
−1
k
, t
T
∗
k
) with t
0
k
= t
k
, t
T
∗
k
= t
k+1
, satisfying
t
ℓ+1
k
− t
ℓ
k
= T
s
for any non-negative integers k and ℓ. Thus,
there are totally T
∗
times state update (iteration) in each time
interval [t
k
, t
k+1
), however, the control inputs will be designed
to only update at the end of the kth iterative process, i.e.,
[t
T
∗
k
, t
T
∗
k
+ ∆t) with ∆t ≪ T
s
. For simplicity, we call T
∗
the
step length of the control input update, and t
T
∗
k
= k · T
∗
· T
s
the terminal time of the system state output.
Then, the discrete-time system states are updated as
V
od
i
(t
ℓ+1
k
) = V
od
i
(t
ℓ
k
) + u
V
i,k
, ω
i
(t
ℓ+1
k
) = ω
i
(t
ℓ
k
) + u
ω
i,k
, (3)
P
i
(t
ℓ+1
k
) = P
i
(t
ℓ
k
) + u
P
i,k
, Q
i
(t
ℓ+1
k
) = Q
i
(t
ℓ
k
) + u
Q
i,k
, (4)
where u
V
i,k
, u
ω
i,k
, u
P
i,k
, and u
Q
i,k
are the distributed voltage,
frequency, active, and reactive power controllers. According to
the droop control principle given in equation (2), the nominal
set points for the ith DER can be derived as
V
nom
i
(t
ℓ+1
k
) = V
od
i
(t
ℓ+1
k
) + K
Q
i
Q
i
(t
ℓ+1
k
)
= V
od
i
(t
ℓ
k
) + K
Q
i
Q
i
(t
ℓ
k
) + u
V
i,k
+ K
Q
i
u
Q
i,k
= V
nom
i
(t
ℓ
k
) + U
V Q
i,k
,
ω
nom
i
(t
ℓ+1
k
) = ω
i
(t
ℓ+1
k
) + K
P
i
P
i
(t
ℓ+1
k
)
= ω
i
(t
ℓ
k
) + K
P
i
P
i
(t
ℓ
k
) + u
ω
i,k
+ K
P
i
u
P
i,k
= ω
nom
i
(t
ℓ
k
) + U
ω P
i,k
,
(5)
where U
V Q
i,k
∆
= u
V
i,k
+ K
Q
i
u
Q
i,k
and U
ωP
i,k
∆
= u
ω
i,k
+ K
P
i
u
P
i,k
are
respectively the control inputs of the nominal set points.
Due to the inherent contradiction between precise voltage
regulation and reactive power sharing in low-voltage MGs,
we mainly focus on the precise voltage regulation. Then, the
reactive power control inputs, u
Q
i,k
, can be adopted from [8,19]
as u
Q
i,k
= −ω
c
Q
i
(t
ℓ
k
) + ω
c
Q
m
i
(t
ℓ
k
), where ω
c
is the cut-off
frequency of the low-pass filters, Q
m
i
is the instantaneous
reactive power components calculated from the measured
output voltage and current, as shown in Fig. 2.
We aim to regulate the voltage magnitudes and frequencies
of all DERs to achieve the desired values and all DERs’
active powers to achieve precise power sharing exactly at
the terminal time t
T
∗
k
, which belongs to a class of desired
finite-time synchronization problem [22]. However, the current
control protocols, stability analysis, and the control objective
are completely different. From this perspective, the proposed
DSC scheme is essentially different from the secondary control
problem considered in [8],[12],[14]. Then, the main objective
4 IEEE TRANSACTIONS ON INDUSTRIAL INFORMATICS, VOL. XX, NO. X, XXX 2016
is to design the discrete-time controllers u
V
i,k
, u
ω
i,k
, and u
P
i,k
such that the system terminal outputs, V
od
i
(t
T
∗
k
), ω
i
(t
T
∗
k
), and
P
i
(t
T
∗
k
), respectively satisfy
lim
k→∞
V
od
i
(t
T
∗
k
) = V
DES
, lim
k→∞
ω
i
(t
T
∗
k
) = ω
DES
, (6)
lim
k→∞
(P
i
(t
T
∗
k
)/P
i,max
− P
j
(t
T
∗
k
)/P
j,max
) = 0, (7)
for all i = j = 1, · · · , N , where P
i,max
is DER
i
’s active
power rating, V
DES
and ω
DES
are the constant desired values
of voltage and frequency, respectively.
Recall Fig. 3, during the kth round iteration, the state vari-
ables, V
od
i
(t), ω
i
(t), and P
i
(t), will be updated at each discrete
time t = t
1
k
, · · · , t
ℓ
k
, · · · , t
T
∗
k
with the invariant control inputs
u
V
i,k
, u
ω
i,k
, and u
P
i,k
, respectively. However, the information
exchanges among DERs (used to constitute the control inputs)
begins at t = t
T
∗
k
and finishes at t = t
T
∗
k
+∆t, then u
V
i,k
, u
ω
i,k
,
and u
P
i,k
needs to be updated subsequently only once.
A. Restoration of Voltage Magnitudes and Frequencies
We design the following discrete-time controllers, u
V
i,k
and
u
ω
i,k
, by incorporating the relative outputs between neighboring
DERs at the terminal time t
T
∗
k
into the updating law
u
V
i,k+1
=
j∈N
V
i
cγ
V
ij
a
V
ij
V
od
j
(t
T
∗
k
) − V
od
i
(t
T
∗
k
)
+cγ
V
i0
a
V
i0
V
DES
− V
od
i
(t
T
∗
k
)
,
u
ω
i,k+1
=
j∈N
ω
i
cγ
ω
ij
a
ω
ij
ω
j
(t
T
∗
k
) − ω
i
(t
T
∗
k
)
+cγ
ω
i0
a
ω
i0
ω
DES
− ω
i
(t
T
∗
k
)
,
(8)
for i = 1, · · · , N, where the weighted adjacency matrices of
voltage and frequency are A
V
= (a
V
ij
)
N×N
∈ [A
V
, A
V
] and
A
ω
= (a
ω
ij
)
N×N
∈ [A
ω
, A
ω
], respectively. The corresponding
leader adjacency matrices are B
V
= diag{a
V
10
, · · · a
V
N0
} ∈
[B
V
, B
V
] and B
ω
= diag{a
ω
10
, · · · a
ω
N0
} ∈ [B
ω
, B
ω
], re-
spectively. c is a positive constant representing the coupling
strength of the cyber-network. Further, the associated gain
matrices are respectively Γ
V
= (γ
V
ij
)
N×N
, Γ
ω
= (γ
ω
ij
)
N×N
,
Ξ
V
= diag{γ
V
10
, · · · , γ
V
N0
}, and Ξ
ω
= diag{γ
ω
10
, · · · , γ
ω
N0
}
that to be deigned.
The distributed voltage and frequency controllers (3) under
control inputs (8) will enable the control objective (6) to
be achieved asymptotically provided certain conditions are
satisfied. Now we derive the conditions.
Denote V
od
= (V
od
1
, · · · , V
od
N
)
T
, ω = (ω
1
, · · · , ω
N
)
T
,
u
V
k
= (u
V
1,k
, · · · , u
V
N,k
)
T
, and u
ω
k
= (u
ω
1,k
, · · · , u
ω
N,k
)
T
, then
rewrite the distributed controllers (3) and control inputs (8) as
V
od
(t
T
∗
k
) = V
od
(t
T
∗
k−1
) + T
∗
u
V
k
,
ω(t
T
∗
k
) = ω(t
T
∗
k−1
) + T
∗
u
ω
k
,
(9)
and
u
V
k+1
= −
c
˜
L
V
+ cB
V
⊙ Ξ
V
V
od
(t
T
∗
k
)
+
cB
V
⊙ Ξ
V
⊗ 1
N
V
DES
,
u
ω
k+1
= −
c
˜
L
ω
+ cB
ω
⊙ Ξ
ω
ω(t
T
∗
k
)
+ (cB
ω
⊙ Ξ
ω
) ⊗ 1
N
ω
DES
,
(10)
where
˜
L
V
and
˜
L
ω
are respectively defined as
˜
l
V
ij
=
q∈N
V
i
a
V
iq
γ
V
iq
, j = i,
−a
V
ij
γ
V
ij
, j = i,
˜
l
ω
ij
=
q∈N
ω
i
a
ω
iq
γ
ω
iq
, j = i,
−a
ω
ij
γ
ω
ij
, j = i.
Combining (9) and (10) gives
˜
V (t
T
∗
k+1
)
˜ω(t
T
∗
k+1
)
=
˜
H
V
O
N×N
O
N×N
˜
H
ω
˜
V (t
T
∗
k
)
˜ω(t
T
∗
k
)
, (11)
where
˜
V = ((V
od
)
T
, V
DES
)
T
, ˜ω = (ω
T
, ω
DES
)
T
,
˜
H
V
= [H
V
, T
∗
(cB
V
⊙ Ξ
V
) ⊗ 1
N
; O
N×1
, 1], and
˜
H
ω
=
[H
ω
, T
∗
(cB
ω
⊙ Ξ
ω
) ⊗ 1
N
; O
N×1
, 1] with H
V
= I
N
−
T
∗
(c
˜
L
V
+cB
V
⊙Ξ
V
) and H
ω
= I
N
−T
∗
(c
˜
L
ω
+cB
ω
⊙Ξ
ω
).
Clearly,
˜
H
V
O
N×N
O
N×N
˜
H
ω
k
=
(
˜
H
V
)
k
O
N×N
O
N×N
(
˜
H
ω
)
k
. If
we can choose the elements of Γ
V
, Ξ
V
, Γ
ω
, and Ξ
ω
, such that
T
∗
j∈
¯
N
V
i
ca
V
ij
γ
V
ij
+ ca
V
i0
γ
V
i0
< 1, ∀i, j = 1, . . . , N,
T
∗
j∈
¯
N
ω
i
ca
ω
ij
γ
ω
ij
+ ca
ω
i0
γ
ω
i0
< 1, ∀i, j = 1, . . . , N,
(12)
then both
˜
H
V
and
˜
H
ω
have only one eigenvalue ρ(
˜
H
V
) =
ρ(
˜
H
ω
) = 1 provided each of the digraphs
ˆ
G(A
V
) and
ˆ
G(A
ω
) contains a spanning directed tree. Thus, it follows from
Lemma 1 in Appendix that
lim
k→∞
˜
H
V
O
N×N
O
N×N
˜
H
ω
k
=
1
N+1
(β
V
)
T
O
N×N
O
N×N
1
N+1
(β
ω
)
T
,
(13)
where β
V
≥ 0 and β
ω
≥ 0 are respectively the normalized
left eigenvectors of
˜
H
V
and
˜
H
ω
corresponding to eigenvalue
1. By the forms of (
˜
H
V
)
k
and (
˜
H
ω
)
k
, we obtain that
1
N+1
β
V
=
∗ ∗
O
N×1
1
, 1
N+1
β
ω
=
∗ ∗
O
N×1
1
.
Then, we get β
V
= (0, · · · , 0, 1)
T
and β
ω
= (0, · · · , 0, 1)
T
,
this together with (11) and (13) give the desired objective (6).
Now we conclude that if the elements of gain matrices, Γ
V
,
Ξ
V
, Γ
ω
, and Ξ
ω
, are selected to satisfy condition (12), then
the designed distributed discrete-time voltage and frequency
controllers (3) with control inputs (8) can restore all DERs’
voltage magnitudes and frequencies in a MG to their desired
values as long as each of the communication digraphs
ˆ
G(A
V
)
and
ˆ
G(A
ω
) contains a spanning directed tree.
B. Active Power Sharing
Since there is no any priori information about the actual
ideal output ratios of the active power for each DER in case of
load changes or the switch of plug and play, the active power
controller is designed without any reference information and is
actually a kind of consensus-based algorithm. We then design
the following discrete-time controller, u
P
i
, by incorporating the
relative active power outputs among neighboring DERs at the
terminal time t
T
∗
k
into the update law:
u
P
i,k+1
=
j∈N
P
i
cγ
P
ij
a
P
ij
K
P
j
P
j
(t
T
∗
k
) − K
P
i
P
i
(t
T
∗
k
)
/K
P
i
,
(14)
for all i = 1, 2, · · · , N , where the weighted adjacency matrix
A
P
= (a
P
ij
)
N×N
∈ [A
P
, A
P
], and the associated gain matrix
is Γ
P
= (γ
P
ij
)
N×N
to be determined.
Similarly, the distributed active power controller (4) under
control inputs (14) will also enable the control objective (7)
