Journal ArticleDOI
Multi-finger turn-on circuits and design techniques for enhanced ESD performance and width scaling
S. Trinh,Markus Paul Josef Mergens,K. Verhaege,Cornelius Christian Russ,John Armer,Phillip Czeslaw Jozwiak,B. Keppens,Russell Mohn,G. Taylor,F. De Ranter,B. Van Camp +10 more
TLDR
In this article, the authors present a very compact ESD protection configuration with an ESD area performance up to 5VHBM/um2 in fully silicided and silicide blocked NMOS designs.About:
This article is published in Microelectronics Reliability.The article was published on 2003-09-01. It has received 51 citations till now.read more
Citations
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Proceedings Article
Boosted and distributed rail clamp networks for ESD protection in advanced CMOS technologies
TL;DR: A new, area efficient, boosted and distributed active MOSFET rail clamp network for I/O pad ESD protection is presented and a compact new rail clamp trigger circuit with high resistance to false triggering is introduced.
Proceedings Article
GGSCRs: GGNMOS Triggered silicon controlled rectifiers for ESD protection in deep sub-micron CMOS processes
Cornelius Christian Russ,Markus Paul Josef Mergens,K. Verhaege,John Armer,Phillip Czeslaw Jozwiak,G. Kolluri,Leslie Ronald Avery +6 more
TL;DR: A novel Grounded-Gate NMOS Triggered SCR device (GGSCR) is introduced and compared to the LVTSCR, demonstrating that GGSCRs can fulfill all ESD protection requirements for todays IC applications in different 0.25 um, 0.18 um and 0.13 um CMOS processes.
Journal ArticleDOI
High holding current SCRs (HHI-SCR) for ESD protection and latch-up immune IC operation
Markus Paul Josef Mergens,Christian C. Russ,Koen Verhaege,John Armer,Phillip Czeslaw Jozwiak,Russ Mohn +5 more
TL;DR: In this article, a Silicon Controlled Rectifier (SCR) for power line and local I/O ESD protection is presented, which exhibits a dual ESD clamp characteristic: low-current high-voltage clamping and high-current low-voltages clamping.
Proceedings ArticleDOI
ESD protection solutions for high voltage technologies
B. Keppens,Markus Paul Josef Mergens,Cong Son Trinh,Cornelius Christian Russ,B. Van Camp,K. Verhaege +5 more
TL;DR: In this article, different case studies are presented for ESD protection based on latch-up immune SCR devices, which is challenging due to narrow ESD design windows, NMOS degradation issues and the creation of unexpectedly weak parasitic devices.
Journal ArticleDOI
Self-Substrate-Triggered Technique to Enhance Turn-On Uniformity of Multi-Finger ESD Protection Devices
Ming-Dou Ker,Jia-Huei Chen +1 more
TL;DR: The turn-on uniformity and ESD robustness of GGNMOS can be greatly improved by the new proposed self-substrate-triggered technique.
References
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Book
ESD in silicon integrated circuits
TL;DR: ESD Phenomena and Test Methods The Physics of ESD Protection Circuit Elements Requirements and Synthesis of ESD Protection Circuits Design and Layout Requirements Analysis and Case Studies Modelling of ESC in Integrated Circuits Effects of Processing and Packaging.
Journal ArticleDOI
Improving the ESD failure threshold of silicided n-MOS output transistors by ensuring uniform current flow
T. Polgreen,Amitava Chatterjee +1 more
TL;DR: In this article, the authors present a model for the failure of the ladder structure n-MOS output device based on both the structure of the device and the behavior of its constituent nMOS transistors.
Proceedings Article
GGSCRs: GGNMOS Triggered silicon controlled rectifiers for ESD protection in deep sub-micron CMOS processes
Cornelius Christian Russ,Markus Paul Josef Mergens,K. Verhaege,John Armer,Phillip Czeslaw Jozwiak,G. Kolluri,Leslie Ronald Avery +6 more
TL;DR: A novel Grounded-Gate NMOS Triggered SCR device (GGSCR) is introduced and compared to the LVTSCR, demonstrating that GGSCRs can fulfill all ESD protection requirements for todays IC applications in different 0.25 um, 0.18 um and 0.13 um CMOS processes.
Proceedings ArticleDOI
Achieving uniform nMOS device power distribution for sub-micron ESD reliability
TL;DR: In this paper, the authors show that by achieving uniform power distribution during the entire ESD event in a large multi-finger nMOS device of 0.6 mu m technology, protection levels in excess of 10 kV can be realized.
Proceedings ArticleDOI
Substrate pump NMOS for ESD protection applications
TL;DR: In this article, a floating guardring is used to pump the local substrate of the protection NMOS to achieve uniform npn protection in a multi-finger NMOS for advanced CMOS technologies with silicide.
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