Split capacitance measurements in thin SOI p-i-n gated diodes are performed and discussed. Contrarily to MOSFETs, the n+ and p+ contacts of the diode supply instantly minority and majority carriers preventing parasitic deep-depletion and transient effects. The gated diode enables accurate characterization from accumulation to strong inversion. We demonstrate that the diode capacitance curves provide extensive information, such as layer thickness and threshold voltage for both n- and p-type MOSFETs simultaneously. The experimental results are validated and explained through numerical simulations.

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Fundamentals of Ultra-Thin-Body MOSFETs and FinFETs: Unique features of UTB MOSFETs

Fully Depleted SOI Characterization by Capacitance Analysis of p-i-n Gated Diodes

The short-channel effects (SCE) in advanced fully depleted silicon-on-insulator MOSFETs are investigated by showing the importance of the intergate coupling. Experimental results highlight that part of the SCE is due to the contribution of the opposite-gate, leading to systematic overestimation of the threshold voltage roll-off and drain-induced barrier lowering (DIBL) effects. Numerical simulations confirm that the impact of back-gate SCE depends on the device structure (film and oxide thickness) and bias. A basic model is presented, which enables the identification of the genuine SCE at each gate. To mitigate or fully cancel the threshold voltage roll-off and DIBL, we propose simple and pragmatic back-biasing schemes.

Fundamentals of Ultra-Thin-Body MOSFETs and FinFETs: Unique features of UTB MOSFETs

Citations

Fully Depleted SOI Characterization by Capacitance Analysis of p-i-n Gated Diodes

Overestimation of Short-Channel Effects Due to Intergate Coupling in Advanced FD-SOI MOSFETs

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