Journal ArticleDOI
Gate-Induced Drain Leakage Reduction in Cylindrical Dual-Metal Hetero-Dielectric Gate All Around MOSFET
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TLDR
In this article, an analytical model of dual-metal hetero-dielectric (DM-HD) cylindrical gate all around (GAA) MOSFET has been proposed to address and solve a substantial issue of gate-induced drain leakage (GIDL) current in order to improve the device reliability, band-to-band tunneling (BTBT), and OFF state leakages.Abstract:
In this paper, an analytical model of dual-metal hetero-dielectric (DM-HD) cylindrical gate all around (GAA) MOSFET has been proposed to address and solve a substantial issue of gate-induced drain leakage (GIDL) current in order to improve the device reliability, band-to-band tunneling (BTBT), and OFF state leakages. The structure is based upon asymmetric gate oxide structure by combining silicon dioxide (SiO2) gate dielectric at source side and vacuum dielectric at drain side, which significantly reduces BTBT and OFF-state gate leakages, thereby making it suitable for low-power applications. It is examined that GIDL i.e., an OFF-state leakage phenomenon, is reduced in DM-HD GAA MOSFET by lowering the BTBT. This can be done by reducing OFF-state leakages due to: 1) increase in tunneling width and 2) increased barrier height from source to channel. The results show that the OFF-state leakage current in DM-HD GAA MOSFET reduces to an order of $10^{-\textsf {13}}$ over $10^{-\textsf {9}}$ A as in the case of conventional GAA MOSFET. The results so obtained are compared with those of cylindrical dual-metal GAA (DM-GAA) MOSFET and GAA MOSFET to analyze its performance. OFF-state leakages at higher temperatures have also been analyzed.read more
Citations
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Journal ArticleDOI
Temperature-Dependent Gate-Induced Drain Leakages Assessment of Dual-Metal Nanowire Field-Effect Transistor—Analytical Model
TL;DR: In this article, an analytical model has been proposed to evaluate the effect of temperature on gate-induced drain leakages (GIDL) in a dual-metal nanowire field effect transistor.
Journal ArticleDOI
Improvement of the long-term stability of ZnSnO thin film transistors by tungsten incorporation using a solution-process method
TL;DR: In this article, the impact of W doping on the film structure, surface morphology, optical properties and chemical compositions of ZTO thin films is analyzed by atomic force microscopy, X-ray diffraction, UV-visible spectroscopy and Xray photoelectron spectrography.
Journal ArticleDOI
High-K Spacer Dual-Metal Gate Stack Underlap Junctionless Gate All Around (HK-DMGS-JGAA) MOSFET for high frequency applications
TL;DR: In this paper, a high-k Spacer based Dual-Metal Gate Stack Junctionless Gate All Around (HK-DMGS-JGAA) MOSFET has been proposed and analyzed for high frequency analog ad RF applications.
Journal ArticleDOI
Shallow Extension Engineered Dual Material Surrounding Gate (SEE-DM-SG) MOSFET for improved gate leakages, analysis of circuit and noise performance
TL;DR: In this article, the authors proposed a Shallow Extension Engineered Dual Material Surrounding Gate (SEE-DM-SG) MOSFET, which creates an insulating layer, which acts as a diffusion stopper and thereby suppresses the off state leakages.
Journal ArticleDOI
Modeling of shallow extension engineered dual metal surrounding gate (SEE-DM-SG) MOSFET gate-induced drain leakage (GIDL)
TL;DR: In this paper, an analytical paradigm for the gate-induced drain leakage (GIDL) for shallow extension engineered dual metal surrounding gate (SEE-DM-SG) MOSFET using superposition technique with appropriate boundary conditions is proposed.
References
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TL;DR: In this paper, Nitrogen implantation of Mo gate was used to fabricate MOS capacitors and CMOS transistors, and a gate work function reduction of 0.42 eV was achieved for the n-FETs on CMOS wafers.
Journal ArticleDOI
Interfacial Charge Analysis of Heterogeneous Gate Dielectric-Gate All Around-Tunnel FET for Improved Device Reliability
Jaya Madan,Rishu Chaujar +1 more
TL;DR: In this article, the impact of interface traps, both donor and acceptor interface charges, present at the Si/SiO2 interface, on analog/RF performance and linearity distortion analysis of heterogeneous-gate-dielectric gate-all-around tunnel FET (HD-GAA-TFET) was investigated.
Journal ArticleDOI
Design for suppression of gate-induced drain leakage in LDD MOSFETs using a quasi-two-dimensional analytical model
TL;DR: In this paper, the gate-induced drain leakage (GIDL) in single-diffusion drain (SD), lightly doped drain (LDD), and fully gate-overlapped LDD (GOLD) NMOSFETs is described.
Proceedings ArticleDOI
Dual material gate field effect transistor (DMGFET)
Wei Long,Ken K. Chin +1 more
TL;DR: The dual material gate field effect transistor (DMGFET) as discussed by the authors is a new type of device, which consists of two laterally contacting materials with different work functions, and it takes advantage of material work function difference in such a way that the threshold voltage near the source is more positive than that near the drain, resulting a more rapid acceleration of charge carriers in the channel and a screening effect to suppress short channel effects.
Journal ArticleDOI
Insight Into Gate-Induced Drain Leakage in Silicon Nanowire Transistors
TL;DR: In this article, detailed physical mechanisms of gate-induced drain leakage (GIDL) in gate-all-around silicon nanowire transistors (SNWTs) are investigated and verified by experiments and TCAD studies.