Delft University of Technology
Graphene Nanoribbon Based Complementary Logic Gates and Circuits
Jiang, Yande; Cucu Laurenciu, Nicoleta; Wang, He; Cotofana, Sorin Dan
DOI
10.1109/TNANO.2019.2903480
Publication date
2019
Document Version
Accepted author manuscript
Published in
IEEE Transactions on Nanotechnology
Citation (APA)
Jiang, Y., Cucu Laurenciu, N., Wang, H., & Cotofana, S. D. (2019). Graphene Nanoribbon Based
Complementary Logic Gates and Circuits.
IEEE Transactions on Nanotechnology
,
18
, 287-298. [8666174].
https://doi.org/10.1109/TNANO.2019.2903480
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IEEE TRANSACTIONS ON NANOTECHNOLOGY, Volume x, xxx
Graphene Nanoribbon Based Complementary Logic
Gates and Circuits
Yande Jiang , Student Member, IEEE, Nicoleta Cucu Laurenciu , Member, IEEE,
He Wang
, Student Member, IEEE, and Sorin Dan Cotofana , Fellow, IEEE
Abstract—As CMOS feature size is r eaching atomic dimensions,
unjustifiable static power, reliability, and economic implications are
exacerbating, thereby prompting for conducting research on new
materials, devices, and/or computation paradigms. Within
this con-
text, graphene nanoribbons (GNRs), owing to graphene’ s excellent
electronic properties, may serve as basic structures for carbon-
based nanoelectronics. In this paper, we make use of the fact that
GNR behavior can be modulated via top/back gate contacts to
mimic a given functionality and combine complementary GNRs
for constructing Boolean gates. We first introduce a generic gate
structure composed of a pull-up GNR perf orming the gate Boolean
function and a pull-down GNR performing its complement. Then,
we seek GNR dimensions and gate topologies required for the de-
sign of 1-, 2-, and 3-input graphene-based Boolean gates, validate
the proposed gates by means of SPICE simulation, which makes
use of a non-equilibrium Green’s function Landauer formalism
based Verilog-A model to calculate GNR conductance, and eval-
uate their performance with respect to propagation delay, power
consumption, and active ar ea footprint. Simulation r esults indicate
that, when compared with 7 nm FinFET CMOS counterparts, the
proposed gates exhibit 6× to 2 orders of magnitude smaller propa-
gation delay , 2 to 3 orders of magnitude lower po wer consumption,
and necessitate 2 orders of magnitude smaller active area footprint.
W e further present full adder (FA) and SRAM cell GNR designs, as
they are curr ently fundamental components for the construction of
any computation system. For an effective FA implementation, we
introduce a 3-input MAJORITY gate, which apart of being able
to directly compute FA’s carry-out is an essential element in the
implementation of error correcting codes codecs, which outper-
forms the CMOS equi v alent carry-out calculation cir cuit by 2 and
3 orders of magnitude in terms of delay and power consumption,
respectively, while requiring 2 orders of magnitude less area. The
proposed FA exhibits 6.2× smaller delay, 3 orders of magnitude
less power consumption, while requiring 2 orders of magnitude
less area, when compared with the 7 nm FinFET CMOS counter-
part. Howev er, because of the effectiv e carry-out circuitry, a GNR-
based n-bit ripple carry adder, whose perf ormance is linear in the
carry-out path, will be 108× faster than an equivalent CMOS im-
plementation. The GNR-based SRAM cell provides a slightly better
resilience to dc-noise characteristics, while performance-wise has
a 3.6× smaller delay, consumes 2 orders of magnitude less power,
and requir es 1 order of magnitude less area than the CMOS equiv-
alent. These results clearly indicate that the proposed GNR-based
The authors are with the Department of Quantum and Computer Engi-
neering, Faculty of Electrical Engineering, Mathematics and Computer Sci-
ence, Delft University of Technology, Delft 2628CD, The Netherlands
(e-mail:, yande.jiang@tudelft.nl; n.cuculaurenciu@tudelft.nl; h.wang-13@
tudelft.nl; s.d.cotofana@tudelft.nl).
approach is opening a promising avenue toward future competitive
carbon-based nanoelectronics.
Index Terms—Graphene, GNR, Graphene-based Boolean Gates,
Carbon-Nanoelectronics.
I. INTRODUCTION
A
S DENNARD scaling nears the limit of atomic feature
size, with in high power density and leakage, low reliabil-
ity and yield, and increased IC production costs, new materials,
structures, and computation paradigms are called upon [1], [2].
Graphene is one of the post Silicon front runners, which has
enjoyed a surge of research popularity in the last decade, open-
ing the way for a wide range of graphene-based applications,
e.g., spintronics, photonics and optoelectronics, sensors, energy
storage and conversion, flexible electronics, and biomedical ap-
plications [3]–[6].
Graphene consists of a single layer of carbon atoms arranged
in a honeycomb lattice, and has a set of unique, remarkable prop-
erties, among which room temperature electron mobility 10×
higher than Si, high thermal conductivity, thinness, and ballistic
carrier transport [7]–[9]. Such properties provide a strong drive
for investigating graphene as a potent contender to Si and to pur-
sue avenues for carbon-based nanoelectronics [10]–[12]. Gen-
erally speaking, the main hindrances to graphene-based logic
circuitry are design and manufacturing related [13], [14].
From the perspective of manufacturing, the principal ambi-
tion is to find a cost-effective, scalable and reliable manufactur-
ing process, which allows mass-production with minimum de-
fect density and highly reproducible features. Over the past few
years, graphene researchers focused on Graphene Nanoribbon
(GNR) fabrication and several approaches have been proposed to
produce GNRs, such as top-down lithographic patterning [15],
[16], chemical procedures [17], and longitudinally unzipping of
high quality grown carbon nanotubes [18], [19]. A fast and in-
expensive approach to fabricate GNRs as narrow as 9 nm with
an ON/OFF current ratio of 70 at room temperature and carrier
mobility of 300 cm
2
v
−1
s
−1
is presented in [20] and a surface-
assisted synthesis method to produce atomically precise, low-
edge-defect GNRs, e.g., 3-Armchair GNRs (1 hexagon width)
and 6-Zigzag GNRs (6 hexagon width) is described in [21]. Such
developments clearly indicate that GNR structures with various
dimensions and geometries can be potentially fabricated in the
close future.
IEEE TRANSACTIONS ON NANOTECHNOLOGY, Volume x, xxx
From the design standpoint, there are several impediments to
graphene-based Boolean logic that need consideration: (i) how
to control the conductivity in order to obtain “on” and “off” states
that are distinguishable, while not compromising the intrinsic
highly advantageous properties of graphene (e.g., high carrier
mobility), (ii) how to encode a specific Boolean logic transfer
function onto electrical properties of graphene (e.g., conduction
maps), (iii) how to find the appropriate external electrical means
(e.g., top gates, back gate) that enable the graphene behaviour
control and that can induce a specific logic functionality, (iv) how
to make sure that digital circuits can be cascaded, i.e., clean and
compatible/matching gate inputs and outputs electric levels, (v)
understanding how the GNRs interact with each other when they
are interconnected, and (vi) how to combine GNRs and construct
graphene-based gates/circuits.
Past work in [22] proved that when a trapezoidal Quantum
Point Contact (QPC) topology [23] is being augmented with top
gates, and when its GNR geometry is changed, the GNR conduc-
tance can be modulated via external voltages such as top gate and
back gate voltages, so that Boolean logic functions behaviour is
being mirrored. This structure addresses the issue outlined in
(i)–(iii), and constitutes a basic ingredient for Boolean gates
construction. However, multiple aspects still need to be taken
into consideration, chiefly, the manner to obtain Boolean gates
which have clean and compatible primary inputs and outputs
voltage levels by shaping and combining various GNRs.
In this paper, we address the (iv)-(vi) issues resulted from the
electrical interaction of GNRs, which will enable the construc-
tion of graphene-based Boolean gates and circuits. For this pur-
pose, we make use of the methodology for designing Boolean
gates by means of two complementary GNRs, i.e., a pull-up
GNR performing the targeted Boolean function and a pull-down
GNR performing its inverse, introduced in [24]. The GNR struc-
tures have a conduction channel made of a graphene zigzag rib-
bon, which is situated between the drain and source contacts.
The gate primary inputs voltages are applied via one/two top
gate/s. Since each gate necessitates GNRs with a desired be-
haviour (e.g., conductance) which corresponds to the Boolean
function that they mimic, we identify topologies which are able
to yield the behaviour of each basic function, i.e., AND, NAND,
OR, NOR, XOR, XNOR, INV, and BUFF. For this purpose, we
conduct a design space exploration with regard to the GNR shape
and its dimensions, and the top gates contacts topology, while
abiding to particular constraints (e.g., gate output voltage values
which are compatible with gate input voltage values, high ratio
between the high and low conductance values of the GNR).
The proposed 1-, 2-, and 3-input GNR gates are validated
in Cadence by means of SPICE simulation which employs a
Verilog-A model, that calls internally a Simulink model in order
to compute the GNR conductance using the Non-Equilibrium
Green’s Function (NEGF)-Landauer formalism [23], [25], [26].
To gain insight into the potential of our proposal, we evaluate the
GNR gates with respect to delay, active area footprint, and power
consumption, relative to the 7 nm FinFET CMOS [27] coun-
terparts. Our results indicate that proposed 1-, 2- and 3-input
graphene gates outperform 7 nm FinFET CMOS counterparts
as follows: (i) they provide up to 6× and 2 orders of magnitude
smaller propagation delay, (ii) they consumes 2 and 3 orders of
magnitude lower power, and (iii) they require 2 orders of mag-
nitude smaller active area footprint, respectively. We observe
that, contrary to CMOS designs, the proposed GNR-based gates
can yield effective power-delay trade-offs, at approximately the
same area. This is because the graphene conductance main con-
tributor is the nanoribbon geometry and its overall topology,
rather than the effective area. Furthermore, the required active
area is not proportional with gate’s function complexity and fan-
in, e.g., XOR and INV have similar footprints, which results in
more compact circuit layout.
We further present GNR based designs of 1-bit Full Adder
(FA) and SRAM cell, as they currently constitute the foundation
for the construction of any computation system. For an effec-
tive FA implementation we design a 3-input MAJORITY gate,
which apart of being able to directly compute FA’s Carry-Out is
an essential element in the implementation of Error Correcting
Codes (ECC) decoders, that outperforms the CMOS equivalent
Carry-Out calculation circuit by 2 and 3 orders of magnitude in
terms of delay (0.109 ps vs 11.863 ps) and power consumption,
respectively, while requiring 2 orders of magnitude less area.
The proposed FA design exhibits 6.2× smaller delay, 3 orders
of magnitude less power consumption, while requiring 2 orders
of magnitude less area, when compared with the 7 nm FinFET
CMOS counterpart. By consequence, a GNR-based n-bit Rip-
ple Carry Adder, which performance is linear in the Carry-Out
path, will be 108× faster than a CMOS implementation. The
GNR based SRAM cell provides a slightly better resilience to
DC noise characteristics, while performance-wise has a 3.6×
smaller delay, consumes 2 orders of magnitude less power, and
requires 1 order of magnitude less area than the CMOS equiva-
lent.
The rest of this paper has the followig structure: Section II
presents the proposed 1-, 2-, and 3-input GNR-based Boolean
gates and their correspondant design methodology. Section III
describes the simulation framework. Section IV and V presents,
evaluates, and compares the proposed designs with state of the
art CMOS equivalents. Finally, the paper ends with some con-
cluding remarks in Section VI.
II. C
OMPLEMENTARY GNR PAIR-BASED BOOLEAN GATES
Subsequently we describe the design methodology we em-
ployed fot the proposed GNR-based Boolean gates and we
present the rationale behind the gates complementary construc-
tion.
We begin by noticing that there are 2 fundamental elements
towards graphene-based circuits: (i) opening the graphene en-
ergy bandgap in order to switch off effectively the current, and
(ii) finding how to control GNR conductance and how to enact
the appropriate electrical response corresponding to a particu-
lar Boolean function. For this purpose, as GNR research vehi-
cle to be build upon, we use a trapezoidal graphene Quantum
Point Contact (QPC) which has zigzag shaped edges [23]. The
GNR can be utilized as conduction channel between the source
and drain contacts, which are biased by a voltage V
d
− V
s
.The
bandgap opening problem can be solved to a certain extent, by
JIANG et al.: GRAPHENE NANORIBBON BASED COMPLEMENTARY LOGIC GATES AND CIRCUITS
Fig. 1. Boolean gate graphene-based building block.
Fig. 2. 2-input XOR conductance map.
carving the GNR geometry. When carving the GNR gometry and
adding top and back gates with various topologies, we can mod-
ulate the graphene conductance (via voltages externally applied
on the GNR top gates), such that it mirrors a particular intended
Boolean function. In Figure 1 is illustrated the main ingredient
employed for the construction of GNR-based Boolean gates,
i.e., a GNR structure which is augmented with 1 back gate and
2 top gates contacts. Figure 2 shows for example, the conduc-
tance map that we obtained for a GNR whose geometry was
optimized in such a way that it is able to reflect the functionality
of the Boolean XOR operator, with 0 V and 1 V associated to
logic low and logic high voltage levels, respectively.
Subsequently, building upon the structure presented in
Figure 1, we propose GNR-based complementary Boolean
gates. For this purpose, we construct each gate using 2 GNR
basic building structures, as depicted in Figure 3: a pull-down
GNR, denoted as GNR
dn
, which has its source terminal con-
nected to the ground V
SS
, and a pull-up GNR, denoted subse-
quently as GNR
up
, which has its drain contact connected to the
supply voltage V
DD
.
Fig. 3. GNR Boolean gate with complementary GNRs.
Fig. 4. GNR topology description parameters.
The pull-up and the pull-down GNRs perform complementary
functions, e.g., a NAND gate is composed of a GNR
up
which
mirrors onto its conductance the NAND logical functionality,
and of a GNR
dn
whose conductance maps the AND logical func-
tionality.
In order to obtain the suitable GNRs for every gate, we conduct
a design space exploration, by changing a set of parameters, as
defined in Figure 4: (i) nanoribbon geometry (i.e., width W and
length L, constriction width W
c
and length L
c
, and extrusion top
length L
b
and width W
b
), and (ii) the topology of the top gate
contacts (i.e., contacts width W
V
g
and their position relative to
the drain and source contacts P
V
g
).
The primary output voltage level of the gate illustrated in
Figure 3, can be approximated as:
V
out
= V
DD
·
G
up
G
dn
+ G
up
, (1)
where G
dn
and G
up
are the conductances of the pull-down and
pull-up GNR, respectively. Therefore, multiple aspects require
to be taken into consideration as part of the design space explo-
ration process, among which:
r
A high ratio between the conductances of the pull-up and
pull-down GNRs is the main contributor for achieving gate
output voltages which are closer to the power supply and
ground rails, as well as low leakage power. In particular,
when the gate output voltage ought to pull-up to V
DD
,
IEEE TRANSACTIONS ON NANOTECHNOLOGY, Volume x, xxx
Fig. 5. GNR shapes for Boolean gates.
the ratio G
up
/G
dn
ought to be at least > 10, for obtain-
ing V
out
≥ 91% · V
DD
. Conversely, when the gate voltage
ought to pull-down to V
SS
, the ratio G
up
/G
dn
ought to be
less than 1/10, for obtaining V
out
≤ 9.1% · V
DD
.
r
To avoid spurious transients in the gate output voltage, the
conductance which is modulated via the gate input voltages
shouldn’t manifest non-linearities.
r
Conductance values which can enable a reasonable input
to output propagation delay and power trade-off are prefer-
able.
r
Balanced output switching delay (i.e., “0” → “1” delay
which resembles “1” → “0” delay).
By means of the design space exploration, we exposed 3 types
of GNR shapes, which are depicted in Figure 5 and found to be
the most suitable for the construction of GNR Boolean gates
construction. Further, in Section IV we prove that by appro-
priately changing the dimensions of the GNR shapes, they de-
liver the necessary functionalities for constructing all the desired
Boolean gates.
We observe that the GNR gates can be directly cascaded to
construct networks of GNR gate to enable GNR-based circuit
design, since the GNRs input voltages are compatible with their
output voltages. Nevertheless, akin to the CMOS case, certain
circuit topologies may result in signal integrity degradations,
and in these situations, buffers, such as the one from Section IV,
are necessary for restoring the logic high and logic low voltage
levels.
III. S
IMULATION SETUP
In this section, we describe the formalism for deriving the
electrical properties of GNRs and present the SPICE simulation
setup of proposed GNR-based Boolean gates.
A. GNR Conduction Computation
To derive GNR conduction under certain bias condition we
model graphene electronic ballistic transport by means of the
Non-Equilibrium Green’s Function (NEGF)-Landauer formal-
ism. The GNR channel is described by a Hamiltonian matrix
H = H
0
+ U, which models the interactions between neigh-
bor carbon atoms (via H
0
), and incorporates all the external as
well as the internal potentials (e.g., top gates voltages, and back
gate voltage) via U. H
0
is constructed by using semi-empirical
(tight-binding) calculations, as follows:
H
0
=
i,j
t
i,j
|ij| , (2)
where t
i,j
=
τ, if atoms i and j are adjacent
0, otherwise.
(3)
In our simulation we account for first nearest-neighbor
(1NN) interactions, with hopping energy between atoms τ =
−2.7eV. The potential distribution matrix U is determined self-
consistently as the solution of the 2D Poisson equation
∇·[(r) ∇U (r)] = −
ρ(r)
0
, (4)
where r = x
ˆ
x + y
ˆ
y is a position vector in space,
0
denotes
the vacuum permittivity, (r) is the dielectric permittivity of
the materials at position r, and ρ represents the net charge den-
sity distribution. The Poisson equation is numerically solved by
making use of the finite difference method. On the two end sides
of the channel, reside the drain and source contacts which have
different electrochemical potentials that sustain the conduction
in the channel. The interactions between the two contacts and
the channel are modelled via the contact self-energy matrices
Σ
1
and Σ
2
, respectively. Once H and Σ
1,2
are computed, the
transmission function T (E), which models the probability of
transmission of one electron from the drain to the source con-
tact, is derived as a function of energy using:
T (E)=Trace
Γ
1
G
R
Γ
2
G
†
R
(5)
where
G
R
(E)=[EI − H − Σ
1
− Σ
2
]
−1
Γ
1,2
= i[Σ
1,2
− Σ
†
1,2
].
The channel current is obtained using the Landauer formula:
I =
q
h
+∞
−∞
T (E) · (f
0
(E − μ
1
) − f
0
(E − μ
2
)) dE, (6)
where f
0
(E) is the Fermi-Dirac distribution function at temper-
ature T , and μ
1,2
denote the Fermi energy of the source and
drain contacts. The conductance can then be written as:
G =
I
V
d
− V
s
. (7)
B. Mixed SPICE-Simulink Simulation
In order to validate the correct operation and evaluate the
proposed GNR-based Boolean gates, we utilize SPICE simu-
lation in Cadence [28]. The GNR of each gate is modeled us-
ing a Verilog-A model which has 5 pins (out of which 2 inout
pins: source and drain, and 3 input pins: 2 top gates and 1 back
gate) [29]. In order to permit multiple GNR shapes and gate
topologies, we developed a parametric Verilog-A model which
is able to take into account: the nanoribbon length L and width
W , the constriction length L
c
and width W
c
, the extrusion top
length L
b
and width W
b
, the position of the top gate contacts
relative to the source/drain contacts P
V
g1,2
, and the top gate con-
tact widths W
V
g1,2
, as defined in Figure 4. The Verilog-A model
triggers internally a Simulink model which computes the GNR
conductance as described in Section III-A. In this way, we ben-
efit of pysics level, accurate results. The inter-communication
