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Proceedings ArticleDOI

Guided multilevel approximation of less significant bits for power reduction

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TLDR
A generic technique, guided multilevel approximation, by which most of the basic arithmetic circuits of a media processing application can be built, and power saving ranging from 30% to 75% is obtained with minimum loss of accuracy.
Abstract
Approximate circuit design has gained significance in recent years targeting applications like media processing where 100% accuracy is not mandatory. Though different approximate adders and multipliers are described in the literature, there is no common approach yet by which many arithmetic circuits can be designed. In this paper we propose a generic technique, guided multilevel approximation, by which most of the basic arithmetic circuits of a media processing application can be built. Basic circuits such as adders, multipliers, filters and multiply-accumulate units are designed using the straight-forward generic technique and power saving ranging from 30% to 75% is obtained with minimum loss of accuracy.

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References
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Accuracy-configurable adder for approximate arithmetic designs

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A low-power, high-performance approximate multiplier with configurable partial error recovery

TL;DR: It is shown that by utilizing an appropriate error recovery, the proposed approximate multiplier achieves similar processing accuracy as traditional exact multipliers but with significant improvements in power and performance.
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MACACO: modeling and analysis of circuits for approximate computing

TL;DR: The results show that MACACO can help a designer to systematically evaluate the impact of approximate circuits, and to choose between different approximate implementations, thereby facilitating the adoption of such circuits for approximate computing.
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Design of voltage-scalable meta-functions for approximate computing

TL;DR: This work proposes design techniques which enable the hardware implementations of these meta-functions to scale more gracefully under voltage over-scaling, and demonstrates that the optimized meta-function implementations consume up to 30% less energy at iso-error rates, while achieving upto 27% lower error rates when compared to their baseline counterparts.
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Low-power high-speed multiplier for error-tolerant application

TL;DR: By introducing accuracy as a design parameter, the bottleneck of conventional digital IC design techniques can be breakthrough to improve on the performances of power consumption and speed.
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