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Journal ArticleDOI

Hardware Trojan Mitigation in Pipelined MPSoCs

TLDR
PMPGuard, a mechanism that detects the presence of hardware Trojans in Third Party Intellectual Property cores of PMPSoCs by continuous monitoring and testing and recovers the system by switching the infected processor core with another one, is presented.
Abstract
Multiprocessor System-on-Chip (MPSoC) has become necessary due to the the billions of transistors available to the designer, the need for fast design turnaround times, and the power wall. Thus, present embedded systems are designed with MPSoCs, and one possible way MPSoCs can be realized is through Pipelined MPSoC (PMPSoC) architectures, which are used in applications from video surveillance to cryptosystems. Hardware Trojans (HTs) on PMPSoCs are a significant concern due to the damage caused by their stealth. An adversary could use HTs to extract secret information (data leakage) to modify functionality/data (functional modification) or make PMPSoCs deny service. In this article, we present PMPGuard, a mechanism that (1) detects the presence of hardware Trojans in Third Party Intellectual Property (3PIP) cores of PMPSoCs by continuous monitoring and testing and (2) recovers the system by switching the infected processor core with another one. We designed, implemented, and tested the system on a commercial cycle accurate multiprocessor simulation environment. Compared to the state-of-the-art system-level techniques that use Triple Modular Redundancy (TMR) and therefore incur at least 3× area and power overheads, our proposed system incurs about 2× area and 1.5× power overheads without any adverse impact on throughput.

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Citations
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Overcoming an untrusted computing base: detecting and removing malicious hardware automatically

TL;DR: This paper proposes BlueChip, a defensive strategy that has both a design-time component and a runtime component that is able to prevent all hardware attacks the authors evaluate while incurring a small runtime overhead.
Journal ArticleDOI

SecureNoC: A Learning-Enabled, High-Performance, Energy-Efficient, and Secure On-Chip Communication Framework Design

TL;DR: The proposed SecureNoC enhances NoC security with several architectural innovations, namely a per-router HT detector, multi-function bypass channels (MBCs), and a lightweight data encryption design which uses an artificial neural network for runtime HT detection with high accuracy.
Journal ArticleDOI

SecureNoC: A Learning-Enabled, High-Performance, Energy-Efficient, and Secure On-Chip Communication Framework Design

TL;DR: SecureNoC as discussed by the authors is a learning-based framework to enhance NoC security against Hardware Trojan (HT) attacks while holistically improving performance and power, which uses an artificial neural network for runtime HT detection with high accuracy.
Journal ArticleDOI

DETON: DEfeating hardware Trojan horses in microprocessors through software ObfuscatioN

TL;DR: Deton as discussed by the authors is an automatic methodology for software manipulation aimed at introducing obfuscation in programs' execution to protect microprocessor-based systems against information stealing HTHs, which can be found in modern and complex microprocessors allowing the attacker to run malicious software, acquire root privileges and to steal secret user information.
Journal ArticleDOI

Hardware Trojan Detection using Transition Probability with Minimal Test Vectors

TL;DR: Simulations performed in the presence of different HT triggers on different benchmark circuits show that the proposed methodology is capable of producing test vectors with significantly improved rare net coverage, compared to an existing technique.
References
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Journal ArticleDOI

SPEC CPU2006 benchmark descriptions

TL;DR: On August 24, 2006, the Standard Performance Evaluation Corporation (SPEC) announced CPU2006, which replaces CPU2000, and the SPEC CPU benchmarks are widely used in both industry and academia.
Journal ArticleDOI

A Survey of Hardware Trojan Taxonomy and Detection

TL;DR: A classification of hardware Trojans and a survey of published techniques for Trojan detection are presented.
Proceedings ArticleDOI

Hardware Trojan detection using path delay fingerprint

TL;DR: A new behavior-oriented category method is proposed to divide trojans into two categories: explicit payload trojan and implicit payloadtrojan, which makes it possible to construct trojan models and then lower the cost of testing.
Journal ArticleDOI

Trustworthy Hardware: Identifying and Classifying Hardware Trojans

TL;DR: A proposed new hardware Trojan taxonomy provides a first step in better understanding existing and potential threats.
Proceedings ArticleDOI

Hardware Trojan: Threats and emerging solutions

TL;DR: The threat posed by hardware Trojans and the methods of deterring them are analyzed, a Trojan taxonomy, models of Trojan operations and a review of the state-of-the-art Trojan prevention and detection techniques are presented.
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