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Journal ArticleDOI

High-performance and simple CMOS interface circuit for differential capacitive sensors

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TLDR
A new concept of current-mode interface circuit for differential-capacitance transducers comprises a capacitance-to-current conversion that enables low-voltage operation, provides both high speed and accuracy, and minimizes post-processing.
Abstract
A new concept of current-mode interface circuit for differential-capacitance transducers is proposed. The solution is suitable for integration and comprises a capacitance-to-current conversion that enables low-voltage operation, provides both high speed and accuracy, and minimizes post-processing.

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Citations
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Journal ArticleDOI

Miniaturized Wireless Sensing System for Real-Time Breath Activity Recording

TL;DR: A portable, non-invasive and easy to operate wireless system has been developed for monitoring the breathing activity of patient and is proposed for monitoring sleep-disordered breathing as well as breathing rhythm of athletes during effort.
Journal ArticleDOI

Current-Mode Capacitive Sensor Interface Circuit With Single-Ended to Differential Output Capability

TL;DR: This paper presents a current-mode interface circuit for capacitive sensors, with the main features being its ability to produce a differential output from a single-ended sensor (using a fixed reference capacitor) and its simplicity in realization.
Journal ArticleDOI

88- A 1-MHz Stray-Insensitive CMOS Current-Mode Interface IC for Differential Capacitive Sensors

TL;DR: The paper describes an innovative technique to implement a low-power high-speed CMOS interface circuit for differential capacitive sensors that exploits an autotuning feedback loop to control the common-mode current, thereby ensuring virtually the same maximum sensitivity and measure accuracy irrespectively of the input parasitic capacitance.
Journal ArticleDOI

Sub-Femto-Farad Resolution Electronic Interfaces for Integrated Capacitive Sensors: A Review

TL;DR: A comprehensive review of the different signal conditioning front-end topologies targeted in particular at sub-femtofarad resolution reveals that resolution, measuring time, area occupation and energy/conversion lower than 100 aF, 1 ms 0.1 mm2, and 100 pJ/conv.
Journal ArticleDOI

Low-Voltage Current-Sensing CMOS Interface Circuit for Piezo-Resistive Pressure Sensor

TL;DR: In this paper, a low-voltage CMOS interface circuit with digital output for piezo-resistive transducers is proposed, which can achieve an equivalent output resolution of 967 bits with less than 023% nonlinearity error.
References
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Journal ArticleDOI

Matching properties of MOS transistors

TL;DR: In this paper, the matching properties of the threshold voltage, substrate factor, and current factor of MOS transistors have been analyzed and measured, and the matching results have been verified by measurements and calculations on several basic circuits.
Journal ArticleDOI

Characterisation and modeling of mismatch in MOS transistors for precision analog design

TL;DR: In this paper, a characterization methodology is presented that accurately predicts the mismatch in drain current over a wide operating range using a minimum set of measured data and the physical causes of mismatch are discussed in detail for both p- and n-channel devices.
Book

Capacitive Sensors: Design and Applications

TL;DR: Capacitive sensors in Silicon Technology as discussed by the authors have been shown to have high dielectric properties of various materials, including electret microphones, acceleration sensors, and sensors with different types of connectors.
Journal ArticleDOI

Charge injection in analog MOS switches

TL;DR: It is shown that this easy-to-handle simplified model, which can be used to implement various strategies to reduce charge injection, is valid in any realistic situation.
Journal ArticleDOI

Random error effects in matched MOS capacitors and current sources

TL;DR: Results indicate that a 9-bit matching accuracy can be obtained for capacitors and an 8-bit accuracy for MOS current sources without difficulty if the systematic error sources are reduced using proper design and layout techniques.
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