Proceedings ArticleDOI
Implementation of single precision floating point multiplier using Karatsuba algorithm
Anand Mehta,C. B. Bidhul,Sajeevan Joseph,P. Jayakrishnan +3 more
- pp 254-256
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TLDR
An efficient floating point multiplier using Karatsuba algorithm that implements the significant multiplication along with sign bit and exponent computations is presented.Abstract:
This paper presents an efficient floating point multiplier using Karatsuba algorithm Digital signal processing algorithms and media applications use a large number of multiplications, which is both time and power consuming We have used IEEE 754 format for binary representation of the floating point numbers Verilog HDL is used to implement Karatsuba multiplication algorithm which is technology independent pipelined design This multiplier implements the significant multiplication along with sign bit and exponent computations Three stage pipelining is being used in the design with the latency of 8 clock cycles In this design, the mantissa bits are divided into three parts of particular bit width in such a way so that the multiplication can be done using the standard multipliers available in FPGA cyclone II device family and synthesized using Altera-Quartus IIread more
Citations
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Implementation of 32 Bit Binary Floating Point Adder Using IEEE 754 Single Precision Format
TL;DR: The objective of this paper is to implement the 32 bit binary floating point adder with minimum time and the design is achieved to increase the operating frequency.
Proceedings ArticleDOI
Design and analysis of single precision floating point multiplication using Karatsuba algorithm and parallel prefix adders
TL;DR: Performance analysis of single precision floating point multiplier is done by using Karatsuba algorithm with Vedic technique for multiplication and different Parallel Prefix adders like Sklansky, Brent-Kung and Knowles adders for exponent addition to provide lesser area to compute multiplication.
Book ChapterDOI
FPGA Implementation of Single-Precision Floating Point Multiplication with Karatsuba Algorithm Using Vedic Mathematics
TL;DR: A high-performance single-precision floating point multiplier is designed based on Karatsuba algorithm with Vedic technique and used different regular adders like carry select, ripple carry adders for exponent addition, which requires less hardware to complete multiplication compared to that existing multipliers.
Journal ArticleDOI
A 16-Bit High-Speed Multiplier Design Based on Karatsuba Algorithm and Urdhva-Tiryagbhyam Theorem Using Modified GDI Cells for Low Power and Area Constraints
Bobby Nelson,Ravi Tiwari +1 more
TL;DR: The paper entails the design of a 16-bit multiplier with the combined application of Karatsuba algorithm and the Urdhva-Tiryagbhyam (UT) theorem and the implementation of the multiplier architecture in Modified-Gate-Diffusion-Input (Mod-GDI) cells for improving the area and power constraints in the proposed novel hybrid multiplier.
Proceedings ArticleDOI
Implementation and Analysis of Single Precision Floating Point Multiplication Using Vedic and Canonic Signed Digit Algorithm
TL;DR: The optimized design methods of CSD multipliers are examined by using different techniques which are used in the above-mentioned multiplier using Vedic to achieve further improvement in the performance of single precision floating point multiplication with Vedic.
References
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What every computer scientist should know about floating-point arithmetic
TL;DR: This paper presents a tutorial on the aspects of floating-point that have a direct impact on designers of computer systems, and concludes with examples of how computer system builders can better support floating point.
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Field programmable gate arrays and floating point arithmetic
Barry Fagin,C. Renard +1 more
TL;DR: An assessment of the strengths and weaknesses of using FPGA's for floating-point arithmetic.
Posted Content
Resource Sharing and Pipelining in Coarse-Grained Reconfigurable Architecture for Domain-Specific Optimization
TL;DR: In this article, the authors proposed a reconfigurable array architecture template and design space exploration flow for domain-specific optimization, which can reduce the hardware cost and the delay without any performance degradation for some application domains.
Proceedings ArticleDOI
Resource Sharing and Pipelining in Coarse-Grained Reconfigurable Architecture for Domain-Specific Optimization
TL;DR: A reconfigurable array architecture template and a design space exploration flow for domain-specific optimization are suggested and Experimental results show that this approach is much more efficient, in both performance and area, compared to existing reconfigured array architectures.
Proceedings ArticleDOI
An efficient implementation of floating point multiplier
TL;DR: An efficient implementation of an IEEE 754 single precision floating point multiplier targeted for Xilinx Virtex-5 FPGA using VHDL to implement a technology-independent pipelined design.
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