Input-parallel Output-series DC-DC Boost Converter with a
Wide Input Voltage Range, for Fuel Cell Vehicles
Ping Wang, Lei Zhou, Yun Zhang, IEEE, Member, Jing Li, IEEE, Member, and Mark Sumner, Senior Member,
IEEE
ABSTRACT: An input-parallel, output-series DC-DC Boost converter
with a wide input voltage range is proposed in this paper. An
interleaved structure is adopted in the input side of this converter to
reduce input current ripple. Two capacitors are connected in series on
the output side to achieve a high voltage-gain. The operating principles
and steady-state characteristics of the converter are presented and
analyzed in this paper. A 400V/1.6kW prototype has been created
which demonstrates that a wide range of voltage-gain can be achieved
by this converter and it is shown that the maximum efficiency of the
converter is 96.62%, and minimum efficiency is 94.14% The
experimental results validate the feasibility of the proposed topology
and its suitability for fuel cell vehicles.
KEY WORDS: Input-parallel output-series; Wide voltage-gain range;
Current ripple; Voltage stress; Fuel cell vehicles.
I. INTRODUCTION
Traditional fossil fuel resources are depleting quickly,
but their continued use contributes to increasing
pollution [1]-[3]. Development of clean energy systems
is essential. Photovoltaic power generation, wind power
generation and fuel cell power generation are important
clean energy technologies [4]-[6]. With regard to
transport, clean-energy vehicles which include fuel cell
vehicles, pure electric vehicles, and hybrid energy source
vehicles can be considered one of the most essential
applications for clean-energy [7]-[8]. Fuel cell vehicles
can provide clean propulsion power with zero emission,
as well as higher energy utilization [9]. However, the use
of fuel cells brings challenges, particularly with their low
output voltage and high output current [10]. The main
DC link bus of fuel cell vehicles has a high voltage level
(400V), making it difficult to directly match voltages
between the fuel cell stack and the main DC link bus.
The fuel cell also has a “soft” output characteristic [11] –
its output voltage varies with load – and it must be
interfaced to the main DC link bus through a step-up
DC-DC converter with a wide range of voltage-gain. In
addition the input current ripple of the converter for fuel
cells must be low enough to prevent accelerated
reduction of the life time of the fuel cell [12].
The conventional DC-DC Boost converter is
employed due to its simple structure, but it suffers from
disadvantages including limited voltage-gain due to
parasitic parameters and the extreme duty cycle, and
high voltage stress for its power semiconductors. The
conventional interleaved Boost DC-DC converter can
obtain low input current ripple, but this converter still
has certain disadvantages including limited voltage-gain
and high voltage stress for power semiconductors. The
voltage stress for power semiconductors in the
three-level DC-DC Boost converter in [13] can be
reduced by half, but its voltage-gain is still limited.
What's more, the output and input sides of this converter
are connected by a diode; the potential difference
between the two sides is a high frequency PWM voltage,
which may result in additional maintenance requirements
and increased EMI. The output and input sides of the
Boost three-level DC-DC converter in [14] share a
common ground, but the voltage-gain of this converter is
still restricted. In addition, this converter requires a
complicated control scheme to balance the
flying-capacitor voltage. The multilevel DC-DC Boost
converter in [15] obtains a high voltage-gain, and low
voltage stress for the power semiconductors. However,
this converter is too complex for automotive applications
and requires reductions in cost and size. The converter
proposed in [16] uses a Z source network to achieve a
higher voltage-gain, but the output and the input sides do
not share a common ground, which may result in
maintenance safety issues and additional EMI. The
Quasi-Z source network is applied to the conventional
Boost DC-DC converter in [17]. This converter, with
high voltage gain also has a high voltage stress for the
power semiconductors. The converter in [18] which
applied a switched-inductor structure, can achieve a high
voltage-gain, but a diode in the converter suffers high
voltage stress. Non-isolated DC-DC converters with
coupled inductors can obtain a high voltage-gain, low
voltage stress for power semiconductors and high
efficiency. There are many types of DC-DC converters
with coupled inductors discussed in [19]-[22]. The
converter with coupled inductors in [19] can obtain a
high voltage-gain and low voltage stress for power
semiconductors, but it suffers high ripple of input current.
Interleaved boost converters with coupled inductors
discussed in [20] have advantages of high voltage-gain
and low input current ripple. However, these converters
have high voltage stress for power semiconductors.
Stacked high step-up coupled-inductor boost converters
discussed in [21] can obtained a very high voltage-gain
and low voltage stress for power semiconductors, but the
input current ripple of these converters are higher. The
interleaved boost converters with
winding-cross-coupling mentioned in [21] obtain a high
voltage-gain, low voltage stress for power
semiconductors and low input current ripple. The
Cascaded boost converters [22] can also obtain a high
voltage-gain, but these converters have high input
current ripple. In addition, their efficiencies are the
product of the efficiency of each stage.
Some of the DC-DC converters described do not
provide low input current ripple, high voltage-gain, and
low voltage stress for power semiconductors at the same
time. In this paper, an input-parallel output-series
DC-DC Boost converter with a wide input voltage range
is proposed as a solution. Compared with the
conventional interleaved DC-DC Boost converter and
the three-level DC-DC Boost converter, this converter
has advantages including low input current ripple, low
voltage stress for power semiconductors, and high
voltage-gain. In addition, the potential difference
between the output and the input sides of this converter
is a capacitor voltage rather than a high frequency PWM
voltage. This paper is organized as follows: in Section II,
the topology of the input-parallel output-series Boost
DC-DC converter is presented. The operating principles
of the converter topology are discussed in Section III. In
Section IV, the steady-state characteristics of the
converter are analyzed. The experimental results and
analysis are given in Section V. Finally, the conclusions
are presented in Section VI.
II. TOPOLOGY OF PROPOSED CONVERTER
The proposed input-parallel output-series DC-DC
Boost converter is shown in Fig. 1. The conventional
DC-DC Boost converter topology can be formed by
inductor L
1
, power switch Q
1
, diode D
1
and capacitor C
2
.
Similarly, inductor L
2
, power switch Q
2
, and capacitors
C
1
and C
3
constitute a Boost DC-DC converter whose
output voltage polarity is opposite to the input voltage
polarity. These two converters are connected in parallel
at the input side and in series at the output side: this
arrangement forms the input-parallel output-series
DC-DC Boost converter.
U
in
L
1
C
3
D
1
Q
1
R
+
-
.
L
2
C
1
D
2
Q
2
C
2
.
.
D
3
.
..
+
-
+
-
+
-
+
-
U
o
+
-
U
Q1
U
Q2
+
-
U
C2
U
C3
U
C1
+
-
U
D2
+
-
U
D3
i
in
i
L1
i
L2
i
Q1
i
Q2
i
D1
+
U
D1
-
i
D2
i
D3
I
o
Fig. 1 The topology of the input-parallel output-series DC-DC Boost
converter.
The topology of the converter comprises 2 inductors,
2 active power switches and 3 diodes. It is assumed that
L
1
=L
2
, C
1
=C
2
=C
3
, U
in
is the input voltage, and i
in
is the
input current. i
Ll
and i
L2
are the currents flowing through
L
1
and L
2
respectively. The currents of Q
1
, Q
2
, D
1
, D
2
,
and D
3
are i
Q1
, i
Q2
, i
D1
, i
D2
, and i
D3
respectively. In
addition, U
D1
, U
D2
, U
D3
, U
C1
, U
C2
, and U
C3
are the
voltage stress of D
1
, D
2
, D
3
, C
1
, C
2
, and C
3
respectively.
U
o
is the output voltage, and I
o
is the output current. An
interleaved structure is adopted in the input side of this
converter to reduce input current ripple. In addition, the
two capacitors at the output side are connected in series
to obtain a high voltage-gain.
III. OPERATING PRINCIPLES
In order to analyze the steady-state characteristics of
the proposed converter, the operation conditions are
assumed to be as follows: (a) all the power
semiconductors and energy storage components are ideal,
which means the on-state resistances of power
semiconductors, the forward voltage drop of the diodes,
and the equivalent series resistances (ESRs) of the
inductors and capacitors are ignored. (b) all the
capacitances are large enough such that each capacitor
voltage can be treated as constant. An interleaved
structure is used in the input side of this converter. In this
case, the relationship between d
1
and d
2
can be written as
d
1
=d
2
=d, where d
1
and d
2
are the duty cycles of Q
1
and
Q
2
respectively. The phase difference between the gate
driving signals of Q
1
and Q
2
is 180°.
According to the operation of Q
1
and Q
2
, when the
proposed converter operates in the continuous
conduction mode (CCM), there are four switching states
described as "S
1
S
2
" in a switching period,
S
1
S
2
={00,01,10,11}. In addition, the sequence of the
switching states in a switching period is related to the
duty cycle ranges of Q
1
and Q
2
. Sequence I
"10-00-01-00-10" appears within the range of 0<d<0.5,
while Sequence II "11-10-11-01-11" is obtained within
the range of 0.5<d<1.
When the proposed converter operated in the
discontinuous conduction mode (DCM), there are seven
switching states in each switching period, S
1
S
2
={01, 10,
11, 10
D
, 01
D
, 00
D1
, 00
D2
}. "10
D
" represents the conditions
of Q
1
is turned on, Q
2
is turned off, and i
L2
=0. "01
D
"
means that Q
1
is turned off, Q
2
is turned on, and i
L1
=0.
"00
D1
" represents that Q
1
and Q
2
are turned off, and i
L1
=0.
"00
D2
" means that Q
1
and Q
2
are turned off, and i
L2
=0. In
addition, Sequence I "10-10
D
-00
D2
-01-01
D
-00
D1
-10"
appears within the range of 0<d<0.5, while Sequence II
"11-10-10
D
-11-01-01
D
-11" can be obtained within the
range of 0.5<d<1. Tab. 1 shows the on-off states of
power semiconductors in each switching state. Energy
flow paths in each switching state of the converter are
shown in
U
in
L
1
C
3
D
1
Q
1
R
+
-
L
2
C
1
D
2
Q
2
C
2
.
.
D
3
.
.
.
+
-
+
-
+
-
+
-
U
o
.
. . .
(a) S
1
S
2
=10
U
in
L
1
C
3
D
1
Q
1
R
+
-
L
2
C
1
D
2
Q
2
C
2
.
D
3
.
.
.
+
-
+
-
+
-
+
-
U
o
..
.
.
.
(b) S
1
S
2
=00
U
in
L
1
C
3
D
1
Q
1
R
+
-
.
.
L
2
C
1
D
2
Q
2
C
2
.
D
3
.
.
.
.
+
-
+
-
+
-
+
-
U
o
.
.
(c) S
1
S
2
=01
U
in
L
1
C
3
D
1
Q
1
R
+
-
.
L
2
C
1
D
2
Q
2
C
2
.
.
D
3
.
.
.
.
.
+
-
+
-
+
-
+
-
U
o
.
(d) S
1
S
2
=11
U
in
L
1
C
3
D
1
Q
1
R
+
-
L
2
C
1
D
2
Q
2
C
2
D
3
.
.
..
+
-
+
-
+
-
+
-
U
o
.
.
.
.
.
(e) S
1
S
2
=10
D
(DCM)
U
in
L
1
C
3
D
1
Q
1
R
+
-
.
L
2
C
1
D
2
Q
2
C
2
.
D
3
.
.
.
+
-
+
-
+
-
+
-
U
o
.
.
.
.
(f) S
1
S
2
=01
D
(DCM)
U
in
L
1
C
3
D
1
Q
1
R
+
-
L
2
C
1
D
2
Q
2
C
2
D
3
.
+
-
+
-
+
-
+
-
U
o
..
.
.
.
.
.
.
(g) S
1
S
2
=00
D1
(DCM)
U
in
L
1
C
3
D
1
Q
1
R
+
-
L
2
C
1
D
2
Q
2
C
2
D
3
.
+
-
+
-
+
-
+
-
U
o
..
.
.
.
.
.
.
(h) S
1
S
2
=00
D2
(DCM)
Fig. 2. The main waveforms for the proposed converter
are given in Fig. 3.
Tab. 1 ON-OFF states of power semiconductors in each switching state
Switching
state S
1
S
2
Q
1
Q
2
D
1
D
2
D
3
10
ON
OFF
OFF
ON
OFF
00
OFF
OFF
ON
ON
OFF
01
OFF
ON
ON
OFF
ON
11
ON
ON
OFF
OFF
ON
10
D
ON
OFF
OFF
OFF
OFF
01
D
OFF
ON
OFF
OFF
ON
00
D1
OFF
OFF
OFF
ON
OFF
00
D2
OFF
OFF
ON
OFF
OFF
U
in
L
1
C
3
D
1
Q
1
R
+
-
L
2
C
1
D
2
Q
2
C
2
.
.
D
3
.
.
.
+
-
+
-
+
-
+
-
U
o
.
. . .
(a) S
1
S
2
=10
U
in
L
1
C
3
D
1
Q
1
R
+
-
L
2
C
1
D
2
Q
2
C
2
.
D
3
.
.
.
+
-
+
-
+
-
+
-
U
o
..
.
.
.
(b) S
1
S
2
=00
U
in
L
1
C
3
D
1
Q
1
R
+
-
.
.
L
2
C
1
D
2
Q
2
C
2
.
D
3
.
.
.
.
+
-
+
-
+
-
+
-
U
o
.
.
(c) S
1
S
2
=01
U
in
L
1
C
3
D
1
Q
1
R
+
-
.
L
2
C
1
D
2
Q
2
C
2
.
.
D
3
.
.
.
.
.
+
-
+
-
+
-
+
-
U
o
.
(d) S
1
S
2
=11
U
in
L
1
C
3
D
1
Q
1
R
+
-
L
2
C
1
D
2
Q
2
C
2
D
3
.
.
..
+
-
+
-
+
-
+
-
U
o
.
.
.
.
.
(e) S
1
S
2
=10
D
(DCM)
U
in
L
1
C
3
D
1
Q
1
R
+
-
.
L
2
C
1
D
2
Q
2
C
2
.
D
3
.
.
.
+
-
+
-
+
-
+
-
U
o
.
.
.
.
(f) S
1
S
2
=01
D
(DCM)
U
in
L
1
C
3
D
1
Q
1
R
+
-
L
2
C
1
D
2
Q
2
C
2
D
3
.
+
-
+
-
+
-
+
-
U
o
..
.
.
.
.
.
.
(g) S
1
S
2
=00
D1
(DCM)
U
in
L
1
C
3
D
1
Q
1
R
+
-
L
2
C
1
D
2
Q
2
C
2
D
3
.
+
-
+
-
+
-
+
-
U
o
..
.
.
.
.
.
.
(h) S
1
S
2
=00
D2
(DCM)
Fig. 2 Energy flow paths in each switching state.
S
1
S
2
t
t
0
0
0
t
t
0
u
Q1
u
Q2
t
0
t
t
0
0
t
0
u
D1
u
D2
u
D3
t
i
L1
i
L2
10
00 00
01
U
o
/2
U
o
/2
U
o
/2
U
o
/2
U
o
/2
0
T
S
dT
s
(1-d)T
s
t
0
i
in
t
2
t
1
t
3
t
4
0
t
I
L1m
I
L2m
I
L1a
I
L2a
.
.
.
.
(a) The main waveforms in the range of 0<d<0.5 (CCM)
S
1
S
2
t
t
0
0
0
t
t
0
u
Q1
u
Q2
t
0
t
t
0
0
t
0
u
D1
u
D2
u
D3
t
i
L1
i
L2
11
10
11
01
U
o
/2
U
o
/2
U
o
/2
U
o
/2
U
o
/2
0
T
S
dT
s
(1-d)T
s
t
0
t
2
t
1
t
3
t
4
0
t
i
in
I
L1n
I
L1b
I
L2n
I
L2b
(b) The main waveforms in the range of 0.5<d<1 (CCM)
S
1
S
2
t
t
0
0
0
t
t
0
u
Q1
u
Q2
t
0
t
t
0
0
t
0
u
D1
u
D2
u
D3
t
t
0
i
L1
i
L2
10 00
D2
01
U
o
/2
U
o
/2
t
2
t
1
t
3
t
4
0
10
D
01
D
00
D1
U
o
/2
U
in
U
o
/2
U
in
U
o
/2
U
o
/2-U
in
U
o
/2-U
in
U
o
/2
U
in
U
o
/2
t
5
t
6
T
S
DT
s
D
2
T
s
I
L1p
I
L2p
(c) The main waveforms in the range of 0<d<0.5 (DCM)
S
1
S
2
t
t
0
0
0
t
t
0
u
Q1
u
Q2
t
0
t
t
0
0
t
0
u
D1
u
D2
u
D3
t
t
0
i
L1
i
L2
11
10
11
01
U
o
/2
U
o
/2
U
o
/2
U
o
/2
U
o
/2
t
2
t
1
t
3
t
4
0
10
D
01
01
D
U
in
U
in
U
o
/2-U
in
U
o
/2-U
in
U
in
T
S
DT
s
D
2
T
s
(d) The main waveforms in the range of 0.5<d<1 (DCM)
Fig. 3 The main waveforms for the proposed converter.
A. CCM operation
When S
1
S
2
=10: power switch Q
1
is turned on and Q
2
is
turned off. Diodes D
1
and D
3
are turned off, while D
2
is
turned on. The energy flow path in this switching state is
shown in
