Patent
Integrated circuit having both vertical and horizontal devices and process for making the same
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TLDR
In this article, all six transistors of an SRAM cell can be formed in a single crystal material for improved device characteristics and increased cell density, which can be seen as an example of vertical integration within semiconductor devices.Abstract:
An integrated circuit (10) has a vertical device, such as a transistor (71), formed by epitaxial growth from a substrate (12) and a horizontal device, such as a transistor (73, 75) grown epitaxially from the vertical device. In accordance with one embodiment of the invention, all six transistors of an SRAM cell can be formed in single crystal material for improved device characteristics and increased cell density. Utilization of various combinations of vertical and horizontal devices permits a large degree of vertical integration within semiconductor devices.read more
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References
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Proceedings ArticleDOI
A surrounding gate transistor (SGT) cell for 64/256 Mbit DRAMs
Kazumasa Sunouchi,Hiroshi Takato,Naoko Okabe,Takashi Yamada,Tohru Ozaki,S. Inoue,Kazuhiko Hashimoto,Katsuhiko Hieda,Akihiro Nitayama,Fumio Horiguchi,F. Masuoka +10 more
TL;DR: In this paper, a novel three-dimensional memory cell called the surrounding gate transistor (SGT) cell has been developed for 64/256-Mb DRAMs (dynamic RAMs).
Patent
Method of formation of transistor and logic gates
TL;DR: In this paper, a plurality of transistors, each in accordance with transistor (10), can be stacked in a vertical manner to form logic gates such as NMOS or PMOS NAND, NOR, and inverter gates.
Journal ArticleDOI
Confined lateral selective epitaxial growth of silicon for device fabrication
Peter J. Schubert,G.W. Neudeck +1 more
TL;DR: An epitaxy technique, confined lateral selective epitaxial growth (CLSEG), which produces wide, thin slabs of single-crystal silicon over insulator, using only conventional processing, is discussed in this article.
Patent
Method for forming a transistor having a dynamic connection between a substrate and a channel region
TL;DR: In this article, a vertically raised transistor (10) is formed having a substrate (12), a conductive plug region (22) is selectively or epitaxially formed to vertically elevate the transistor, and a first doped region (16a and 16b) and a second doped regions (16b) are each electrically coupled to the conductively plug region via sidewall contacts.
Patent
Semiconductor memory cell having a trench structure
Craig S. Lage,Richard D. Sivan +1 more
TL;DR: In this article, a semiconductor memory cell (10) having a trench (24) and access transistor (54) formed in a well region (20) was shown to be coupled to ground and power signals by buried layers (12, 18) in the substrate.