Low-Area wallace multiplier
Shahzad Asif,Yinan Kong +1 more
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TLDR
Synthesis results show that the proposed multiplier has the lowest area as compared to other tree-based multipliers, without compromising on the speed of the original Wallace multiplier.Abstract:
Multiplication is one of the most commonly used operations in the arithmetic Multipliers based on Wallace reduction tree provide an area-efficient strategy for high speed multiplication A number of modifications are proposed in the literature to optimize the area of the Wallace multiplier This paper proposed a reduced-area Wallace multiplier without compromising on the speed of the original Wallace multiplier Designs are synthesized using Synopsys Design Compiler in 90 nm process technology Synthesis results show that the proposed multiplier has the lowest area as compared to other tree-based multipliers The speed of the proposed and reference multipliers is almost the sameread more
Citations
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Proceedings ArticleDOI
Low power wallace tree multiplier using modified full adder
TL;DR: A modified full adder using multiplexer is proposed to achieve low power consumption of multiplier and shows an average reduction of 37.45% in power consumption, 45.75% in area, and 17.65% in delay compared to the existing approaches.
Journal ArticleDOI
A self-perturbed pseudo-random sequence generator based on hyperchaos
TL;DR: A self-perturbed pseudorandom sequence generator based on hyper-chaotic system to overcome the problem of chaotic degradation and is suitable to be used in privacy encryption and secure communication.
Proceedings ArticleDOI
Design of delay efficient modified 16 bit Wallace multiplier
TL;DR: Conventional Array Multipliers and Dadda Multiplier are compared with the Wallace multiplier in terms of delay and a proposed sixteen bit Wallace multiplier is implemented by using Carry Select Adder (CSLA) and Binary to Excess -1 Converter (BEC) adder.
Proceedings ArticleDOI
Design of area and power efficient digital FIR filter using modified MAC unit
TL;DR: A novel scheme for the design of an area and power efficient digital finite impulse response (FIR) filter for digital signal processing (DSP) application's is studied and results show that the Area Delay Product of the proposed 5-tap and 9-tap filter gains an improvement over the conventional method.
Proceedings ArticleDOI
Low power array multiplier using modified full adder
TL;DR: In this paper, a modified full adder using multiplexer is proposed to achieve low power consumption of multiplier, which can reduce the number of partial products generated in a multiplication process.
References
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C.R. Baugh,Bruce A. Wooley +1 more
TL;DR: An algorithm for high-speed, two's complement, m-bit by n-bit parallel array multiplication is described, which is converted to an equivalent parallel array addition problem in which each partial product bit is the AND of a multiplier bit and a multiplicand bit.
Journal ArticleDOI
Conditional-Sum Addition Logic
TL;DR: A comparison of several adders shows that, within a set of stated assumptions, conditional-sum addition is superior in certain respects, including processing speed.