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Journal ArticleDOI

Metal‐Catalyzed Etching of Vertically Aligned Polysilicon and Amorphous Silicon Nanowire Arrays by Etching Direction Confinement

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TLDR
In this paper, a systematic study of metal-catalyzed etching of (100), (110), and (111) silicon substrates using gold catalysts with three varying geometrical characteristics was carried out.
Abstract
A systematic study of metal-catalyzed etching of (100), (110), and (111) silicon substrates using gold catalysts with three varying geometrical characteristics: isolated nanoparticles, metal meshes with small hole spacings, and metal meshes with large hole spacings is carried out. It is shown that for both isolated metal catalyst nanoparticles and meshes with small hole spacings, etching proceeds in the crystallographically preferred direction. However, the etching is confined to the single direction normal to the substrate surface when a catalyst meshes with large hole spacings is used. We have also demonstrated that the metal catalyzed etching method when used with metal mesh with large hole spacings can be extended to create arrays of polycrystalline and amorphous vertically aligned silicon nanowire by confining the etching to proceed in the normal direction to the substrate surface. The ability to pattern wires from polycrystalline and amorphous silicon thin films opens the possibility of making silicon nanowire array-based devices on a much wider range of substrates.

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Citations
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Journal ArticleDOI

Metal-assisted chemical etching of silicon and nanotechnology applications

TL;DR: In this article, the metal-assisted chemical etching of silicon, a low-cost and versatile method enabling fine control over morphology feature of silicon nanostructures, is summarized.
Journal ArticleDOI

Assembly of one dimensional inorganic nanostructures into functional 2D and 3D architectures. Synthesis, arrangement and functionality

TL;DR: This critical review is intended to provide an interesting starting point to view the current state of the art and show perspectives for future developments in this field, focusing on selected nanomaterials and the possibilities for building three dimensional arrays starting from one dimensional building blocks.
Patent

Photosensitive imaging devices and associated methods

TL;DR: In this paper, photosensitive devices and associated methods are provided, for example, a photosensitive imager device can include a semiconductor substrate having multiple doped regions forming at least one junction, a textured region coupled to the semiconductor substrategies and positioned to interact with electromagnetic radiation, and an electrical transfer element coupled to an electrical substrate and operable to transfer an electrical signal from the at least 1 junction.
Patent

Silicon-based visible and near-infrared optoelectric devices

TL;DR: In this article, a silicon photodetector with a surface layer that is doped with sulfur inclusions with an average concentration in a range of about 0.5 atom percent to about 1 5 atom percent was presented.
Journal ArticleDOI

Uniform Vertical Trench Etching on Silicon with High Aspect Ratio by Metal-Assisted Chemical Etching Using Nanoporous Catalysts

TL;DR: An innovated MaCE method, which combined the use of a nanoporous gold thin film as the catalyst and a hydrofluoric acid-hydrogen peroxide mixture solution with a low HF-to-H2O2 concentration ratio as the etchant, marks a breakthrough in high-quality silicon trench-etching technology with a cost of more than 2 orders of magnitude lower than that of the currently available methods.
References
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Journal ArticleDOI

Nanowire Nanosensors for Highly Sensitive and Selective Detection of Biological and Chemical Species

TL;DR: The small size and capability of these semiconductor nanowires for sensitive, label-free, real-time detection of a wide range of chemical and biological species could be exploited in array-based screening and in vivo diagnostics.
Journal ArticleDOI

Enhanced thermoelectric performance of rough silicon nanowires

TL;DR: In this article, the authors report the electrochemical synthesis of large-area, wafer-scale arrays of rough Si nanowires that are 20-300 nm in diameter.
Journal Article

Enhanced Thermoelectric Performance in Rough Silicon Nanowires

TL;DR: Electrochemical synthesis of large-area, wafer-scale arrays of rough Si nanowires that are 20–300 nm in diameter show promise as high-performance, scalable thermoelectric materials.
Journal ArticleDOI

High Performance Silicon Nanowire Field Effect Transistors

TL;DR: In this article, the influence of source-drain contact thermal annealing and surface passivation on key transistor properties was examined, and it was shown that thermal annaling and passivation of oxide defects using chemical modification can increase the average transconductance from 45 to 800 nS and average mobility from 30 to 560 cm 2 /V
Journal ArticleDOI

Crystalline-amorphous core-shell silicon nanowires for high capacity and high current battery electrodes.

TL;DR: It is demonstrated here that these core-shell nanowires have high charge storage capacity with approximately 90% capacity retention over 100 cycles and show excellent electrochemical performance at high rate charging and discharging.
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