Proceedings ArticleDOI
Minimizing core supply noise in a power delivery network by optimization of decoupling capacitors using simulated annealing
Jai Narayan Tripathi,Pratik Damle,Rakesh Malik +2 more
- pp 1-3
TLDR
In this paper, an optimal decoupling network is designed by Simulated Annealing to reduce the power supply noise in power delivery networks, which reduces the cumulative impedance of power delivery network.Abstract:
An efficient methodology for minimizing core supply noise in Power Delivery Networks is presented. To reduce the power supply noise, an optimal decoupling network is designed by Simulated Annealing. The cumulative impedance of Power Delivery Network is reduced using lesser number of decoupling capacitors compared to placing decoupling capacitors intuitively. The supply noise is minimized according to the requirement of system specifications and the corresponding jitter reduction is reported.read more
Citations
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Journal ArticleDOI
A Radial Basis Function Network-Based Surrogate-Assisted Swarm Intelligence Approach for Fast Optimization of Power Delivery Networks
TL;DR: In this article , a novel approach using surrogate assisted swarm intelligence is presented for efficient and fast optimization of power delivery networks, where the decoupling capacitors are selected and placed optimally, eventually reducing the cumulative impedance of the PDN below the target impedance.
A Domain Decomposition Approach for Assessment of Decoupling Capacitors in Practical PDNs
TL;DR: In this article , a domain decomposition method is proposed to evaluate the effectiveness of decoupling capacitors in practical power delivery networks (PDNs), based on the separation of a PDN into its local and non-local domains.
Journal ArticleDOI
Computational Intelligence Based Selection and Placement of Decoupling Capacitors: A Comparative Study
TL;DR: In this paper , a computational intelligence-based generic framework is presented to solve the industrial problem of decoupling capacitor optimization in a practical power delivery network using metaheuristic algorithms.
Proceedings ArticleDOI
On-Interposer Decoupling Capacitors Placement for Interposer-based 3DIC
TL;DR: In this paper , an efficient simulated Annealing (SA) based algorithm is proposed to perform decap placement automatically on the interposer, where the target impedance can be achieved within a certain frequency range.
References
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Book
Engineering Optimization: An Introduction with Metaheuristic Applications
TL;DR: The author highlights key concepts and techniques for the successful application of commonly-used metaheuristc algorithms, including simulated annealing, particle swarm optimization, harmony search, and genetic algorithms.
Book
Power Integrity Modeling and Design for Semiconductors and Systems
Madhavan Swaminathan,A.E. Engin +1 more
TL;DR: This book's system-level focus and practical examples will make it indispensable for every student and professional concerned with power integrity, including electrical engineers, system designers, signal integrity engineers, and materials scientists.
Journal ArticleDOI
Efficient In-Package Decoupling Capacitor Optimization for I/O Power Integrity
TL;DR: It is shown that impedance metric leads to large overdesign and then a noise-driven optimization algorithm for decoupling capacitors in packages for power integrity is developed and reduced by 3times and more than 10times faster even with explicit noise computation.
Journal ArticleDOI
GA-optimized decoupling capacitors damping the rectangular power-bus' cavity-mode resonances
TL;DR: In this article, the authors proposed a GA to find the decoupling capacitors for suppressing the cavity-mode resonances in the printed circuit board power-bus structure, where the optimal positions and circuital values of decoupled capacitors are efficiently determined to selectively mitigate specific resonance peaks.
Journal ArticleDOI
Optimization for the Locations of Decoupling Capacitors in Suppressing the Ground Bounce by Genetic Algorithm
TL;DR: In this paper, the optimal placement of decoupling capacitors in suppressing the input and transfer impedances of power-ground planes was investigated in high-speed digital printed circuit boards.