Journal ArticleDOI
Optimization for the Locations of Decoupling Capacitors in Suppressing the Ground Bounce by Genetic Algorithm
TLDR
In this paper, the optimal placement of decoupling capacitors in suppressing the input and transfer impedances of power-ground planes was investigated in high-speed digital printed circuit boards.Abstract:
In the high-speed digital printed circuit board, decoupling capacitors play an important role in lowering the power-ground planes impedance leading to the ground bounce noise in I/O ports while the logic is in transition. This paper investigates the optimal placement of decoupling capacitors in suppressing the input and transfer impedances of power-ground planes. The cavity model combines with genetic algorithm (GA) here to find the design specification and the optimal placement of the decoupling capacitors.read more
Citations
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Journal ArticleDOI
Overview of Power Integrity Solutions on Package and PCB: Decoupling and EBG Isolation
TL;DR: In this article, the authors reviewed possible solutions based on decoupling or isolation for suppressing power distribution network (PDN) noise on package or printed circuit board (PCB) levels.
Journal ArticleDOI
Decoupling Capacitor Placement in Power Delivery Networks Using MFEM
TL;DR: In this article, a genetic algorithm is used for the selection and placement of decoupling capacitors in a power distribution network (PDN) to reduce the effort expended by the complex task of capacitance placement.
Journal ArticleDOI
Multipin Optimization Method for Placement of Decoupling Capacitors Using a Genetic Algorithm
Ihsan Erdin,Ramachandra Achar +1 more
TL;DR: A genetic algorithm (GA)-based method is proposed for simultaneous optimization of decoupling capacitors assigned to multiple pins of a ball-grid array (BGA) package on a printed circuit board and a noise susceptibility parameter is introduced as the basis of a new set of GA fitness functions.
Proceedings ArticleDOI
Automatic package and board decoupling capacitor placement using genetic algorithms and M-FDM
TL;DR: An automatic capacitor placement optimization method that relies on a genetic algorithm to provide a stochastic search of the design space, while employing an efficient core PDN simulator based on the multi-layer finite difference method (M-FDM).
Journal ArticleDOI
Multi-Objective Optimization of Decoupling Capacitors for Placement and Component Value
Ihsan Erdin,Ramachandra Achar +1 more
TL;DR: The proposed approach provides options for designers to meet power integrity specifications by employing uniform-valued capacitors that help to reduce the bill-of-material (BOM) cost and mitigate the part procurement risk.
References
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Journal ArticleDOI
Genetic algorithms in engineering electromagnetics
J.M. Johnson,V. Rahmat-Samii +1 more
TL;DR: This paper presents a tutorial and overview of genetic algorithms for electromagnetic optimization, showing genetic-algorithm optimization to be suitable for optimizing a broad class of problems of interest to the electromagnetic community.
Journal ArticleDOI
Modeling and transient simulation of planes in electronic packages
TL;DR: In this paper, a plane pair structure is first characterized in terms of its impedance (Z) matrix at arbitrary port locations in the frequency domain, then extended for multiple plane pairs under the assumption that skin effect is prominent at higher frequencies causing isolation between the layers.
Journal ArticleDOI
Faster Computation of Z-Matrices for Rectangular Segments in Planar Microstrip Circuits (Short Paper)
A. Benalla,K.C. Gupta +1 more
TL;DR: In this paper, the authors present an analytical treatment of one of the summations involved in the doubly infinite series in the corresponding Green's function, which can be used to accelerate the computation of Z-matrices for planar microstrip circuits.
Journal ArticleDOI
Estimating the power bus impedance of printed circuit boards with embedded capacitance
Minjia Xu,Todd H. Hubing +1 more
TL;DR: In this article, the authors employ a simple cavity model to investigate the features affecting the power bus impedance of printed circuit boards with embedded capacitance, which is an alternative to discrete decoupling capacitors and achieved by enhancing the natural capacitance between closely spaced power and return planes.