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Journal ArticleDOI

Selection and placement of decoupling capacitors in high speed systems

TLDR
In this paper, the authors focus on damping cavity mode effects in power delivery networks by the particle swarm optimization technique and find the optimal capacitors and their locations on the board using the presented methodology.
Abstract
The Power Integrity problem for high speed systems is discussed in context of selection and placement of decoupling capacitors. Power Integrity is maintained by damping the cavity mode peaks at resonant frequencies using decoupling capacitors. This article focuses on damping cavity mode effects in power delivery networks by the particle swarm optimization technique. The s-parameter data of power plane geometry and capacitors are used for the accurate analysis including bulk capacitors and VRM, for a real world problem. The optimal capacitors and their locations on the board are found using the presented methodology, which can be used for similar power delivery networks in high speed systems.

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Citations
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Proceedings ArticleDOI

Minimizing core supply noise in a power delivery network by optimization of decoupling capacitors using simulated annealing

TL;DR: In this paper, an optimal decoupling network is designed by Simulated Annealing to reduce the power supply noise in power delivery networks, which reduces the cumulative impedance of power delivery network.
Journal ArticleDOI

PCB Decoupling Optimization With Variable Number of Capacitors

TL;DR: An approach based on the combination of time-domain contour integral method and optimization with variable number of dimensions is introduced and works with models having variable dimensions and searches for the optimal one.
Proceedings ArticleDOI

Optimal Design of a Decoupling Network Using Variants of Particle Swarm Optimization Algorithm

TL;DR: In this paper, a practical case study is presented, where, in order to design an efficient PDN, the cumulative impedance of the PDN is optimized below the target impedance.
Proceedings ArticleDOI

Modeling and mitigation on conducted emission for switch mode power supply

TL;DR: In this paper, two methods have been designed to reduce the conducted emission (CE) of switch mode power supply (SMPS), such as the capacitor shunt between the source and drain electrodes of MOSFET and the capacitors matrix.
Journal Article

Modeling and Mitigation on Conducted Emission for Switch Mode Power Supply

TL;DR: In this paper, the voltage division factor, isolation factor and impedance under SMPS side of artificial mains network have been studied based on high frequency parasitic parameters to analyze the conducted emission (CE) measurement uncertainty.
References
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Journal ArticleDOI

High-frequency characterization of power/ground-plane structures

TL;DR: In this article, the authors describe a strategy to characterize power and groundplane structures using a full cavity-mode frequency-domain resonator model, and introduce a novel technique to suppress modal impedances, minimizing both transfer and input impedances.
Book

Power Integrity Modeling and Design for Semiconductors and Systems

TL;DR: This book's system-level focus and practical examples will make it indispensable for every student and professional concerned with power integrity, including electrical engineers, system designers, signal integrity engineers, and materials scientists.
Journal ArticleDOI

Analog circuit design optimization through the particle swarm optimization technique

TL;DR: The practical suitability of PSO to solve both mono-objective and multiobjective discrete optimization problems and the aptness ofPSO to optimize difficult circuit problems, in terms of numbers of parameters and constraints is shown.
Journal ArticleDOI

Modeling of simultaneous switching noise in high speed systems

TL;DR: In this article, the authors present an efficient method to model the SSN for high speed systems by developing circuit models for the planes and interconnections that can be combined using superposition theory.
Journal ArticleDOI

Efficient In-Package Decoupling Capacitor Optimization for I/O Power Integrity

TL;DR: It is shown that impedance metric leads to large overdesign and then a noise-driven optimization algorithm for decoupling capacitors in packages for power integrity is developed and reduced by 3times and more than 10times faster even with explicit noise computation.
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