JOURNAL OF LIGHTWAVE TECHNOLOGY, VOL. 23, NO. 1, JANUARY 2005
401
Nanophotonic Waveguides in Silicon-on-Insulator
Fabricated With CMOS Technology
Wim Bogaerts, Member, IEEE, Member, OSA, Roel Baets, Senior Member, IEEE, Member, OSA,
Pieter Dumon, Student Member, IEEE, Vincent Wiaux, Stephan Beckx, Dirk Taillaert, Student Member, IEEE,
Bert Luyssaert, Student Member, IEEE, Joris Van Campenhout, Student Member, IEEE,
Peter Bienstman, Member, IEEE, and Dries Van Thourhout, Member, IEEE
Abstract—High-index-contrast, wavelength-scale structures are
key to ultracompact integration of photonic integrated circuits.
The fabrication of these nanophotonic structures in silicon-on-in-
sulator using complementary metal–oxide–seminconductor
processing techniques, including deep ultraviolet lithography, was
studied. It is concluded that this technology is capable of com-
mercially manufacturing nanophotonic integrated circuits. The
possibilities of photonic wires and photonic-crystal waveguides
for photonic integration are compared. It is shown that, with
similar fabrication techniques, photonic wires perform at least an
order of magnitude better than photonic-crystal waveguides with
respect to propagation losses. Measurements indicate propagation
losses as low as 0.24 dB/mm for photonic wires but 7.5 dB/mm for
photonic-crystal waveguides.
Index Terms—Nanophotonics, photonic crystal, waveguides, sil-
icon-on-insulator (SOI).
I. INTRODUCTION
I
NTEGRATION of a multitude of photonic functions onto
a single chip can bring the same advantages to photonics
as what integration has done for microelectronics: a serious
reduction of costs through high-yield wafer-scale processes,
increased performance, compact components with complex
functionality, etc. In photonic integrated circuits (PICs) on-chip
integration has the added benefit of automatically meeting
the critical alignment tolerances of subcomponents through
the lithographic processes. This reduces the need for active
alignment methods, which are notorious for dominating the
cost of discrete optoelectronic components. Today’s photonic
components, however, are typically too large to allow much
integration. Many components have a length scale of several
Manuscript received February 2, 2004; revised June 22, 2004. This work was
supported in part by the European Union through the IST-PICCO project. Part
of this work was carried out in the context of the Belgian IAP-PHOTONnetwork
project. The work of W. Bogaerts, P. Dumon, and B. Luyssaert was supported
in part by the Flemish Institute for the Industrial Advancement of Scientific and
Technological Research (IWT) under a specialization grant. The work of J. Van
Campenhout was supported in part by the Flemish Fund for Scientific Research
(FWO-Vlaanderen) under a doctoral fellowship. The work of P. Bienstman was
supported in part by the Flemish Fund for Scientific Research (FWO-Vlaan-
deren) under a postdoctoral fellowship. The work of D. Van Thourhout was
supported in part by the Belgian Federal Office for Scientific, Technical and
Cultural Affairs.
W. Bogaerts, R. Baets, P. Dumon, D. Taillaert, B. Luyssaert, J. Van Camp-
enhout, P. Bienstman, and D. Van Thourhout are with the Department of In-
formation Technology, Interuniversity Microelectronics Center (IMEC), Ghent
University, 9000 Gent, Belgium (e-mail: wim.bogaerts@intec.ugent.be).
V. Wiaux and S. Beckx are with Silicon Processing Technology Division,
IMEC vzw, 3001 Leuven, Belgium.
Digital Object Identifier 10.1109/JLT.2004.834471
hundred micrometers to several millimeters and, in some
cases, even several centimeters, and this is not only true for
active functions, but also for simple passive components such
as filters, (de)multiplexers, and even simple interconnecting
waveguides with bends, couplers, and splitters.
In many cases, these large dimensions are needed because
one uses waveguides with a low refractive index contrast. By
increasing this index contrast, the confinement can be improved,
but this also means that the waveguide core should be reduced
in size to keep the waveguide single mode. Then, however, the
geometrical features not only become very small but have to be
very accurately fabricated, with an accuracy in the range of 1 to
10 nm. Therefore, we can call these waveguides
nanophotonic
waveguides. To confine light in a nanophotonic waveguide, one
can use total internal reflection, as in conventional waveguides,
creating so-called photonic wires. However, it is also possible
to use a high-contrast periodic structure, a photonic crystal,to
confine light by the photonic bandgap (PBG) effect [1], [2].
A consequence of the higher lateral index contrast is that
the waveguides become more sensitive to scattering at rough-
ness on the core–cladding interface [3]. Therefore, high-quality,
high-resolution fabrication tools are required for these nanopho-
tonic waveguides. For research purposes, nanophotonic com-
ponents are traditionally fabricated using e-beam lithography.
While this is a very accurate technique, it is a serial writing
process, making it slow and unsuitable for mass fabrication. Al-
ternatively, conventional optical lithography, with illumination
wavelengths down to 300 nm, is used for the fabrication of cur-
rent photonic integrated circuits (ICs) but lacks the resolution
to define dense nanophotonic structures like photonic crystals
and photonic wires. Deep ultraviolet (UV) lithography, the tech-
nology used for advanced complementary metal–oxide–sem-
inconductor (CMOS) fabrication, offers both the required res-
olution and the throughput needed for commercial applications.
However, technology development for 248, 193, and recently
157 nm is driven by the CMOS industry, and processes are there-
fore not always suited for nanophotonic structures.
In this paper, nanophotonic waveguides will be demonstrated
in silicon-on-insulator (SOI) fabricated with deep UV lithog-
raphy. For this purpose, standard CMOS fabrication processes
were adopted to improve their capability for fabricating photonic
nanostructures, like photonic crystals and photonic wires. This
fabrication process is described in detail in Sections II–V. A
number of nontrivial obstacles that had to be overcome in order
to migrate the process from CMOS to nanophotonics are also
0733-8724/$20.00 © 2005 IEEE
402 JOURNAL OF LIGHTWAVE TECHNOLOGY, VOL. 23, NO. 1, JANUARY 2005
discussed. Then, a number of fabricated waveguide components
and measurements of the propagation losses are discussed in Sec-
tion VI and VII. Finally, Section VIII will offer some examples
of other nanophotonic structures fabricated with this technique.
II. SOI N
ANOPHOTONIC
WAVEGUIDES
In nanophotonic integrated circuits, waveguides are an ex-
tremely crucial component. Not only are they necessary for in-
terconnects, but many functional elements are also based on
waveguides. Therefore, good waveguides are a prerequisite for
further integration.
A. General Properties
For waveguides that guide light through total internal re-
flection, the confinement is largely determined by the contrast
in the refractive index between the waveguide core and the
surrounding cladding. A high refractive index contrast in the
lateral direction (2:1 or higher) makes it possible to confine
the light tightly to the waveguide core. In semiconductor ma-
terial systems, this can be achieved by etching the waveguides
deeper into the semiconductor substrate. However, as the index
contrast increases, the waveguide will support more guided
modes, which is an unwanted effect in most PICs. To obtain a
single-mode waveguide with a high refractive index contrast,
the waveguide’s cross section must be reduced, to the order of
, with the wavelength of the light in vacuum, and
the refractive index of the waveguide core. For very high
contrasts, like semiconductor
to air or
semiconductor to silica
, waveguides have widths
smaller than 500 nm, with features that can be as small as 100
nm when operating at telecom wavelengths between 1.3 and 1.6
m. The use of the high refractive index contrast implies that
the geometrical features not only become very small (100–500
nm) but also have to be very accurately fabricated, sometimes
down to 1 nm.
There are two techniques to confine light in nanophotonic
waveguides, which are commonly known as photonic wires and
photonic crystals. A photonic wire is basically a conventional
waveguide with a high index contrast and a small cross section,
typically with a width of 300–500 nm. The light is guided by
total internal reflection. The tight confinement allows for com-
pact elements, like sharp bends, corner mirrors [4], and ring res-
onators [5]. However, the performance is limited by the scat-
tering at sidewall roughness, so these waveguides require very
good processing. Alternatively, light can be guided in a pho-
tonic-crystal slab. Photonic crystals are periodic structures with
a high refractive index contrast and a period of the order of the
wavelength of the light in the material [1], [6]. Because of this
strong contrast and the periodicity, photonic crystals have pe-
culiar optical properties, including a PBG [2]. A line defect in
a photonic crystal then effectively creates a waveguide, as the
light cannot leak away into the crystal.
B. Material Choice: SOI
We can use a variety of materials for photonic-crystal slabs,
as long as the refractive index contrast is sufficiently high. Semi-
conductors, with refractive indexes typically larger than 3, are
ideally suited. For the majority of this work, we chose SOI. The
main reasons for this choice are its very good optical properties
at optical fiber communications wavelengths and its compati-
bility with CMOS fabrication processes, which is discussed in
Section III.
SOI consists of a thin silicon layer on top of an oxide cladding
layercarriedonabaresiliconwafer.Withitssiliconcore
and its oxide cladding , it has a high vertical refractive
indexcontrast. Inaddition, boththesilicon andtheoxide aretrans-
parent at telecom wavelengths of 1.3 and 1.55
m.
To reduce leakage of the guided mode in the top layer to the
silicon substrate, we chose an oxide thickness of 1
m [7]. The
thickness of the core was chosen to be 220 nm in order to keep
the slab waveguide single mode for the transverse-electric (TE)
polarization.
C. Photonic Crystals
Photonic crystals are periodic structures with periods of the
order of the wavelength of the light and a very high refractive
index contrast within each period [2], [6]. For telecommunica-
tions, where infrared light with wavelengths in the range 1.3–1.6
m are used, the photonic-crystal period is typically 0.5 m
or less. The periodicity can extend in one, two, or three dimen-
sions. Because of this high refractive index contrast, light will
be scattered very strongly throughout the structure, and the scat-
tered waves from each period can either add up or cancel out,
depending on the wavelength of the light. For a well-chosen ge-
ometry and a unit cell with sufficiently high refractive index con-
trast, the scattering from each cell can interfere in such a way
that all light inside the crystal within a certain wavelength range
is canceled out, so no propagation is possible in the structure [1],
creating a PBG.
As already mentioned, a defect can introduce localized states
in the PBG, binding the light in a specific location in the crystal.
In a line defect, light has no other option than to follow the de-
fect, which defines a perfect waveguide. The light cannot leak
away through the surrounding photonic crystal because of the
PBG. Therefore, if reflection is controlled, bends in such pho-
tonic-crystal waveguides can, in principle, be very abrupt.
Although three-dimensional (3-D) photonic crystals can con-
trol light in all directions, they are very difficult to fabricate for
optical and infrared wavelengths. An alternative to full 3-D pho-
tonic crystals is the combination of a conventional waveguide
structure and a photonic crystal. Here, a two-dimensional (2-D)
photonic crystal is created by etching holes or rods in a semicon-
ductor layer structure. In the horizontal direction, the photonic
crystal controls the flow of light, while in the vertical direction
the light is confined in the layer with the higher refractive index.
These photonic crystal slabs also provide 3-D control of light
while they are much easier to fabricate, using lithography and
etching techniques. The bottom row of Fig. 1 shows examples
of a single-line-defect waveguide (a so-called W1 waveguide)
in a photonic-crystal slab made in SOI. Unlike 3-D photonic
crystals, the confinement in the vertical direction is not neces-
sarily perfect, which can result in out-of-plane scattering and
can cause leakage of light [8], [9].
When the concept of photonic-crystal waveguides was intro-
duced, the design of a waveguide seemed as simple as removing
BOGAERTS et al.: NANOPHOTONIC WAVEGUIDES IN SOI 403
Fig. 1. Nanophotonic waveguides in SOI. Top: Photonic wires. Bottom: W1
photonic-crystal waveguide. Left: Deep ething. Right: Silicon-only etch.
a row of holes, creating a so-called W1 waveguide. While this
design has indeed a guided-waveguide mode, its properties are
ill-suited for pure waveguiding. A simple W1 waveguide in SOI
is not a very good waveguide. It is not single mode, and the
guided modes have a narrow bandwidth below the light line.
However, by removing the oxide cladding in SOI, and thus cre-
ating a membrane, the light line of the cladding is shifted to
higher frequencies. In this way, a W1 waveguide with sufficient
bandwidth is possible, and waveguides with very low propaga-
tion losses (less than 1 dB/mm) have been demonstrated both in
silicon membranes [10], [11] and in GaAs membranes [12].
Without oxide removal, Notomi
et al. have already demon-
strated low propagation losses by reducing the optical volume
of the core. In such a W0.7 waveguide, the width of the wave-
guide has been decreased by shifting the lattice regions on both
sides [11], [13], making the waveguide single mode. However,
the shifted lattice makes it more difficult to implement bends
or splitters. Alternative ways to reduce the optical volume of
the waveguide core without shifting the lattice, like introducing
defect holes or a defect trench, or increasing the size of the
border holes, invariably introduce additional sidewall surface,
increasing the possibility of scattering at sidewall roughness [3].
Apart from pure waveguiding, photonic-crystal slabs can also
be used for other purposes. One significant aspect of periodic
structures is the appearance of wavelength regions with a very
flat dispersion curve, and therefore a low group velocity, espe-
cially near the band edges [14]. In these regions, light is coupled
strongly between the backward- and forward-propagating direc-
tion and travels slowly through the waveguide. If the waveguide
has active properties, like gain or nonlinear effects, the interac-
tion time of the light with the material is significantly enhanced
when using slow waves.
D. Photonic Wires
The principle of photonic wires is the same as of conventional
optical waveguides: light is confined in a narrow core of high
index material surrounded by a cladding of lower index mate-
rial. For photonic wires, the index contrast between core and
cladding is very high. This gives rise to very strong confinement,
which makes it possible to make very sharp bends without radi-
ation losses in the bend. However, there is no PBG to stop light
from radiating away once it escapes the confinement of the wire.
Photonic wires are not periodic, and therefore their disper-
sion relation is far less exotic than photonic crystals. This makes
them more predictable and easy to design. Moreover, they are
broad-band with a fairly linear dispersion, making them very
well suited for waveguiding.
E. Deep or Shallow Etching
When we want to fabricate nanophotonic components in SOI,
we can choose between two etch procedures, each with its merits
and drawbacks. Fig. 1 illustrates both procedures for a photonic-
crystal slab and a photonic wire. When we etch both the top sil-
icon and the underlying oxide, we increase the refractive index
contrast even more, because we replace the oxide
with air . In addition, the bottom of the photonic-crystal
holes are far removed from the guided mode, eliminating a pos-
sible source of scattering. An additional advantage is that the
vertical layer structure becomes more symmetric, reducing the
interaction between TE and transverse-magnetic (TM) modes.
However, as we will illustrate in Section III, this approach in-
troduces significantly more sidewall roughness, which is a prin-
cipal source of propagation losses.
When listing all these advantages of deep etching, is there any
reason to etch only the silicon, as illustrated in the right part of
Fig. 1? When we etch only the silicon, the sidewall roughness
due to etching can be significantly reduced. In addition, in order
to eliminate the interaction between TE and TM, oxide can be
deposited on top of the silicon core after etching. This deposi-
tion, briefly discussed in Section III, works better with shallow
holes than with deep holes.
A third option is to remove the oxide substrate altogether.
This lowers the refractive index of the lower cladding signifi-
cantly, and increases the design flexibility for photonic-crystal
waveguides. However, this membrane approach has a major
drawback. Because the waveguide structure has to be free-
standing, this can only be used on a limited area. Photonic
crystals, with their interconnected network, are much better
suited for this approach than photonic wires.
F. Conclusion
The reduced size and the high index contrast make the design
of nanophotonic waveguides a nontrivial issue. While photonic
crystals offer a wide selection of strong dispersive properties,
it is not straightforward to design a simple waveguide. On
the other hand, the dispersive properties, together with the
strong confinement, make the structures very promising for
wavelength-selective functionality.
For simple waveguides, photonic wires are better suited.
Their behavior is very predictable, and it is easy to make
compact elementary waveguide components, like bends and
splitters. However, wires are sensitive to sidewall roughness,
more so than photonic crystals. Therefore, very good fabrica-
tion quality is needed.
404 JOURNAL OF LIGHTWAVE TECHNOLOGY, VOL. 23, NO. 1, JANUARY 2005
III. FABRICATION
WITH ADVANCED
CMOS P
ROCESSES
In this section, we will describe the fabrication of nanopho-
tonic waveguides with deep UV lithography and dry etching.
These techniques are based on advanced CMOS processes, like
the ones used in the high-end semiconductor industry.
A. Differences Between CMOS and Nanophotonic Structures
While deep UV lithography is capable of printing features
with the dimensions of photonic wires and photonic crystals,
there are some significant differences between nanophotonic
components and typical CMOS components: CMOS compo-
nents are layered structures. Each layer contains only critical
structures of a certain type (transistor gates, contact holes, etc.),
so the process can be optimized for each layer individually. In
planar nanophotonics, all structures are fabricated on the same
level, and small alignment tolerances require that all structures
are fabricated in the same lithography step. Photonic crystals
and photonic wires are very different structures, and the optimal
process conditions differ between them. Therefore, process op-
timization for nanophotonic components will have to make dif-
ferent compromises than for CMOS structures. As we will see
further, it is not straightforward to fabricate both photonic wires
and photonic crystals on target at the same time.
In addition, the types of structures can differ significantly. For
example, the optimal photonic-crystal lattice for TE polariza-
tion is a triangular lattice of air holes where the holes have a
large fill factor, i.e., the hole diameter is a significant fraction of
the pitch [2]. We call these superdense lattices, i.e., where the
hole diameter is larger than the spacing in between. This type
of structure is not used in electronics, where the best equivalent
in CMOS is a 1:1 dense (i.e., hole diameter equal to the spacing
in between) array of contact holes used to connect the different
metal interconnect layers. However, these contact holes are typ-
ically arranged in a square lattice, and the hole diameter never
exceeds half of the pitch.
In addition, the requirements for sidewall roughness are very
different in nanophotonics and in CMOS. In the former, all
sidewalls should be kept smooth to reduce scattering, while in
CMOS structures, the effect of line-edge roughness is felt only
in narrow lines in the electrical resistance of the line. This has
only recently become an issue for CMOS fabrication.
B. SOI Wafers
Apart from being a good material for photonic waveguides,
SOI is also compatible with CMOS processes and commer-
cially available in 200 mm wafers. High-quality SOI wafers
are typically fabricated using wafer bonding. For our experi-
ments, we used commercial wafers from SOITEC fabricated
with the UNIBOND process [15]. First, a wafer is oxidized to
create the buried oxide layer. Then, hydrogen ions are implanted
at a well-controlled depth, creating a Smart Cut. This wafer is
bonded to a clean silicon wafer. The substrate of the first wafer
can now be separated along the Smart Cut interface and then
annealed and polished.
First experiments with standard UNIBOND wafers (a buried
oxide of 400 nm and a top silicon layer of 205 nm) showed that
the oxide was too thin, causing optical leakage to the substrate
Fig. 2. Process flow for the fabrication of nanophotonic structures in SOI. The
third and fourth row illustrate two options for the etching of the structures, either
through both silicon and oxide, or only the silicon layer. (a) Bare wafer, (b)
resist coating and soft bake, (c) top AR coating, (d) exposure, (e) postexposure
bake, (f) development, (g) silicon etch, (h) oxide etch, (i) resist strip, (g’) resist
hardening, (h’) silicon etch, and (i’) resist strip.
[7]. Therefore, we switched to custom-made wafers with a sil-
icon thickness of 220 nm and an oxide layer of 1
m. This buffer
thickness provides adequate isolation from the substrate for the
TE polarization.
C. Overview of the Fabrication Process
The fabrication process with deep UV lithography is sim-
ilar to that of conventional optical projection lithography. The
basic process flow is illustrated in Fig. 2. First, the photoresist
is coated on top of a 200-mm SOI wafer and then prebaked. On
top of the resist, an antireflective (AR) coating is spun to elimi-
nate reflections at the interface between the air and the photore-
sist. These reflections could give rise to standing waves in the
photoresist, and therefore inhomogeneous illumination. Then,
the wafer is sent to the stepper, which illuminates the photore-
sist with the pattern on the mask. As a 200-mm wafer can con-
tain many structures, the die with the pattern is repeated across
the wafer. This can be done with varying exposure conditions,
which makes it possible to do detailed process characterization.
After lithography, the resist goes through a postexposure bake
and is then developed. For our experiments, we used Shipley
UV3 resist.
Depending on whether we want the bottom oxide-etched or
not, we can use different processes. If we want to etch the un-
derlying oxide, the developed photoresist can be used directly
BOGAERTS et al.: NANOPHOTONIC WAVEGUIDES IN SOI 405
as an etch mask (third row of Fig. 2). The top silicon layer and
the oxide are then etched subsequently in different etch cham-
bers but without exposing the structures to the atmosphere in
between the etch processes.
However, to reduce the sidewall roughness, our optimized
fabrication process does not include the oxide etch (bottom row
of Fig. 2). Instead, an additional plasma treatment of the devel-
oped photoresist is needed, called
resist hardening, before the
etching (see Section V). Then, the photoresist is used directly
as a mask for the silicon etch. In addition, a number of postpro-
cessing steps are possible, including thermal oxidation or oxide
deposition.
IV. D
EEP
UV LITHOGRAPHY
For research purposes, e-beam lithography is the workhorse
for the fabrication of photonic nanostructures. Unfortunately,
this technique is not suitable for commercial application. There-
fore, we explored the possibilities of using deep UV lithog-
raphy. For our experiments, we had access to the CMOS fabrica-
tion equipment of IMEC (the Inter University Microelectronics
Center), Leuven, Belgium. Because lithography at a wavelength
of 248 nm is now the mainstream fabrication tool for high-end
CMOS, we chose this wavelength for the majority of our fabri-
cation runs. We used an ASML PAS5500/750 stepper connected
to an automated track for preprocessing (coating and baking)
and postprocessing (baking and developing).
A. Resolution
In optical projection lithography, like deep UV lithography,
the resolution is largely determined by the illumination wave-
length
and the numerical aperture (NA) of the projection
system [16]. The most critical structures are the dense periodic
ones, where the smallest period
that can be imaged is
given by
NA
(1)
when the first diffraction order of the periodic structure is still
passed through the projection system. The loss of the higher
diffraction orders will result in a fuzzy image. The final quality
of the resist patterns is therefore determined by the threshold
of the photoresist and the exposure dose. For example, when
printing holes, the hole diameter will increase when a larger
exposure energy is used in the stepper. In practice, this means
that with 248-nm lithography and an NA
, we can make
structures with a period down to 400 nm.
B. Lithography of Nanophotonic Structures
Early experiments with CMOS masks, discussed in [7], show
how we can use this exposure dose to print holes larger than
originally designed. Using this overexposure, we could print
superdense lattices with a mask containing just 1:1 dense pat-
terns. After these successful tests, masks were designed with
nanophotonic test structures and components. Fig. 3 shows the
feature size of typical nanophotonic waveguide structures as a
function of exposure dose. As we can see, the hole diameters of
Fig. 3. Size of nanophotonic structures as a function of exposure dose. Top:
Triangular lattices of holes with different design pitches and diameters (on the
mask). Designed diameter: Pitch ratio is 0.4 (circles), 0.6 (squares), and 0.8
(triangles). Bottom: Isolated lines with different design linewidth.
the triangular lattices increases with the exposure dose, while
the linewidth of a photonic wire decreases. The range of expo-
sure energies where the structure is still within specification is
called the exposure latitude.
On the other hand, with a given feature size on the mask,
we can print a wide range of feature sizes on the wafer. As the
exposure conditions can be changed by the stepper from die to
die, we can fabricate a wealth of different features on a single
wafer.
C. Combining Lines and Holes
One of the difficulties of fabricating nanophotonic compo-
nents is the requirement to print both photonic wires (isolated
lines) and photonic crystals (superdense lattices of holes) to-
gether in the same lithography step. As we can deduce from the
graphs in Fig. 3, the dose-to-target for lines and holes is quite
different. Therefore, when targeting to fabricate a lattice of holes
correctly, there will always be a bias on the isolated lines, which
will be overexposed and therefore too narrow.
In order to print the lines correctly, a bias needs to be ap-
plied in the design to either the holes or the lines to print both
together on target [7]. Because it is easier to change the design
size of an isolated structure, the bias is best applied to the lines.
For example, at the dose of 25 mJ, where 300-nm holes with
500-nm pitch print correctly, a 50-nm bias needs to be applied
to a 500-nm line to print it correctly. This correction should be
known in advance, because it needs to be applied directly on