Proceedings ArticleDOI
Noise-tolerant dynamic circuit design
Lei Wang,Naresh R. Shanbhag +1 more
- Vol. 1, pp 549-552
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TLDR
A new noise-tolerant dynamic circuit technique is presented, and the average noise threshold energy (ANTE) and the energy normalized ANTE metrics are proposed for quantifying the noise immunity and energy efficiency of circuit techniques.Abstract:
Noise in deep submicron technology combined with the move towards dynamic circuit techniques for higher performance have raised concerns about reliability and energy efficiency of VLSI systems in the deep submicron era. To address this problem, a new noise-tolerant dynamic circuit technique is presented. In addition, the average noise threshold energy (ANTE) and the energy normalized ANTE metrics are proposed for quantifying the noise immunity and energy efficiency, respectively, of circuit techniques. Simulation results in 0.35 micron CMOS for NAND gate designs indicate that the proposed technique improves the ANTE and energy normalized ANTE by 2.54X and 2.25X over the conventional domino circuit. The improvement in energy normalized ANTE is 1.22X higher than the existing noise-tolerance techniques. A full adder design based on the proposed technique improves the ANTE and energy normalized ANTE by 3.7X and 1.95X over the conventional dynamic circuit. In comparison, the static circuit improves ANTE by 2.2X but degrades the energy normalized ANTE by 11%. In addition, the proposed technique has a smaller area overhead (69%) as compared to the static circuit whose area overhead is 98%.read more
Citations
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Journal ArticleDOI
Design of Robust, Energy-Efficient Full Adders for Deep-Submicrometer Design Using Hybrid-CMOS Logic Style
TL;DR: The proposed full adder is energy efficient and outperforms several standard full adders without trading off driving capability and reliability and is based on a novel xor-xnor circuit that generates xor and xnor full-swing outputs simultaneously.
Journal ArticleDOI
Toward achieving energy efficiency in presence of deep submicron noise
R. Hegde,Naresh R. Shanbhag +1 more
TL;DR: Information-theoretic lower bounds on energy consumption of noisy digital gates and the concept of noise tolerance via coding for achieving energy efficiency in the presence of noise are presented.
Journal ArticleDOI
On circuit techniques to improve noise immunity of CMOS dynamic logic
Li Ding,Pinaki Mazumder +1 more
TL;DR: It is demonstrated through analysis and simulation that using the proposed method the noise tolerance of dynamic logic gates can be improved beyond the level of static CMOS logic gates while the performance advantage of dynamic circuits is still retained.
Journal ArticleDOI
Design methodologies for high-performance noise-tolerant XOR-XNOR circuits
TL;DR: Novel methodologies for designing energy-efficient noise-tolerant exclusive-OR-exclusive- NOR circuits that can operate at low-supply voltages with good signal integrity and driving capability are proposed and prove to be faster and successfully work at all ranges of supply voltage.
Proceedings ArticleDOI
Noise tolerant low voltage XOR-XNOR for fast arithmetic
TL;DR: Results using 0.18m CMOS technology and HSPICE for simulation show that the proposed XOR-XNOR circuit is more noise-immune and displays better power-delay product characteristics than the compared circuit.
References
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