Proceedings ArticleDOI
On minimization of test power through modified scan flip-flop
Satyadev Ahlawat,Jaynarayan Tudu +1 more
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TLDR
Through bypassing the slave latch during loading/unloading operation the proposed design eliminates redundant switching activity in combinational logic and hence minimizes test power and the functional performance overhead is comparatively very less than the previously proposed output gating techniques.Abstract:
Power dissipation during scan testing of modern high complexity designs could be many folds higher than the functional operation power, which is a well established observation. High test power dissipation can severely affect the chip yield and hence the final cost of the product. This makes it of utmost important to develop low power scan test methodologies. In this work we have proposed a modified scan flip-flop design which uses a low cost dynamic slave latch to shift the test vectors and allows the static slave latch to retain the responses from the previous test vector. Through bypassing the slave latch during loading/unloading operation the proposed design eliminates redundant switching activity in combinational logic and hence minimizes test power. Furthermore the proposed scan flip flop design does not use any gating element in functional path, and hence the functional performance overhead is comparatively very less than the previously proposed output gating techniques so far.read more
Citations
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Journal ArticleDOI
A Statistic-Based Scan Chain Reordering for Energy-Quality Scalable Scan Test
TL;DR: An energy-quality (EQ) scalable scan test method using new scan chain reordering that achieved lower energy consumption and relieve the routing overhead on ISCAS’89, ITC’99, and IWLS’05 OpenCores benchmark circuits in most cases compared with previously existing methods without excessive runtime overhead.
Journal ArticleDOI
Approximate Scan Flip-flop to Reduce Functional Path Delay and Power Consumption
TL;DR: In this article , the authors proposed two scan flip-flop designs using 10 nm FinFET technology to address the problem of mux-induced delay and internal power.
Proceedings ArticleDOI
Designof Efficient Scan Flip-Flop
B Nagesh,B S Nikhil Chandra +1 more
TL;DR: In this paper, two novel and efficient scan flip-flop designs have been implemented consuming less power, area and delay, and an improvement of 42.12% and 27.38% was observed in speed during functional and test modes respectively.
Patent
Double edge triggered mux-d scan flip-flop
TL;DR: In this paper, a family of low power, min-drive strength, double-edge triggered (DET) input data multiplexer (Mux-D) scan flip-flop (FF) is provided.
References
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Proceedings ArticleDOI
Minimized power consumption for scan-based BIST
TL;DR: The design modifications include some gating logic for masking the scan path activity during shifting, and the synthesis of additional logic for suppressing random patterns which do not contribute to increase the fault coverage.
Proceedings ArticleDOI
Preferred Fill: A Scalable Method to Reduce Capture Power for Scan Based Designs
TL;DR: Experimental results presented for benchmark and industrial circuits demonstrate the effectiveness of the proposed method called Preferred Fill to reduce average and peak power dissipation during capture cycles of launch off capture delay fault tests.