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Journal ArticleDOI

Parallelism-Aware Batch Scheduling: Enhancing both Performance and Fairness of Shared DRAM Systems

Onur Mutlu, +1 more
- Vol. 36, Iss: 3, pp 63-74
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TLDR
A parallelism-aware batch scheduler that seamlessly incorporates support for system-level thread priorities and can provide different service levels, including purely opportunistic service, to threads with different priorities, and is also simpler to implement than STFM.
Abstract
In a chip-multiprocessor (CMP) system, the DRAM system isshared among cores. In a shared DRAM system, requests from athread can not only delay requests from other threads by causingbank/bus/row-buffer conflicts but they can also destroy other threads’DRAM-bank-level parallelism. Requests whose latencies would otherwisehave been overlapped could effectively become serialized. As aresult both fairness and system throughput degrade, and some threadscan starve for long time periods.This paper proposes a fundamentally new approach to designinga shared DRAM controller that provides quality of service to threads,while also improving system throughput. Our parallelism-aware batchscheduler (PAR-BS) design is based on two key ideas. First, PARBSprocesses DRAM requests in batches to provide fairness and toavoid starvation of requests. Second, to optimize system throughput,PAR-BS employs a parallelism-aware DRAM scheduling policythat aims to process requests from a thread in parallel in the DRAMbanks, thereby reducing the memory-related stall-time experienced bythe thread. PAR-BS seamlessly incorporates support for system-levelthread priorities and can provide different service levels, includingpurely opportunistic service, to threads with different priorities.We evaluate the design trade-offs involved in PAR-BS and compareit to four previously proposed DRAM scheduler designs on 4-, 8-, and16-core systems. Our evaluations show that, averaged over 100 4-coreworkloads, PAR-BS improves fairness by 1.11X and system throughputby 8.3% compared to the best previous scheduling technique, Stall-Time Fair Memory (STFM) scheduling. Based on simple request prioritizationrules, PAR-BS is also simpler to implement than STFM.

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Citations
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Studying the impact of hardware prefetching and bandwidth partitioning in chip-multiprocessors

TL;DR: This paper proposes an analytical model-based study to investigate how hardware prefetching and memory bandwidth partitioning impact CMP system performance and how they interact, and finds several interesting observations that can be valuable for future C MP system design and optimization.
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BWS: balanced work stealing for time-sharing multicores

TL;DR: BWS (Balanced Work Stealing) is presented, a work-stealing scheduler for time-sharing multicore systems that leverages new, lightweight operating system support and improves system throughput and fairness via two means.
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A programmable memory controller for the DDRx interfacing standards

TL;DR: The proposed controller is evaluated by mapping previously proposed DRAM scheduling, address mapping, refresh scheduling, and power management algorithms onto PARDIS, a programmable memory controller that can meet the performance requirements of a high-speed DDRx interface.
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Predictive coordination of multiple on-chip resources for chip multiprocessors

TL;DR: A predictive yet cost effective mechanism for multiple resource management in CMP that uses a set of hardware-efficient online profilers and an analytical performance model to predict the application's performance with different intra-core and/or inter-core resource allocations.
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Virtual machine consolidation based on interference modeling

TL;DR: This work proposes a performance model that considers interferences in the shared last-level cache and memory bus and presents a virtual machine consolidation method called swim which is based on the interference model.
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