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Journal ArticleDOI

Parallelism-Aware Batch Scheduling: Enhancing both Performance and Fairness of Shared DRAM Systems

Onur Mutlu, +1 more
- Vol. 36, Iss: 3, pp 63-74
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TLDR
A parallelism-aware batch scheduler that seamlessly incorporates support for system-level thread priorities and can provide different service levels, including purely opportunistic service, to threads with different priorities, and is also simpler to implement than STFM.
Abstract
In a chip-multiprocessor (CMP) system, the DRAM system isshared among cores. In a shared DRAM system, requests from athread can not only delay requests from other threads by causingbank/bus/row-buffer conflicts but they can also destroy other threads’DRAM-bank-level parallelism. Requests whose latencies would otherwisehave been overlapped could effectively become serialized. As aresult both fairness and system throughput degrade, and some threadscan starve for long time periods.This paper proposes a fundamentally new approach to designinga shared DRAM controller that provides quality of service to threads,while also improving system throughput. Our parallelism-aware batchscheduler (PAR-BS) design is based on two key ideas. First, PARBSprocesses DRAM requests in batches to provide fairness and toavoid starvation of requests. Second, to optimize system throughput,PAR-BS employs a parallelism-aware DRAM scheduling policythat aims to process requests from a thread in parallel in the DRAMbanks, thereby reducing the memory-related stall-time experienced bythe thread. PAR-BS seamlessly incorporates support for system-levelthread priorities and can provide different service levels, includingpurely opportunistic service, to threads with different priorities.We evaluate the design trade-offs involved in PAR-BS and compareit to four previously proposed DRAM scheduler designs on 4-, 8-, and16-core systems. Our evaluations show that, averaged over 100 4-coreworkloads, PAR-BS improves fairness by 1.11X and system throughputby 8.3% compared to the best previous scheduling technique, Stall-Time Fair Memory (STFM) scheduling. Based on simple request prioritizationrules, PAR-BS is also simpler to implement than STFM.

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Citations
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Dissertation

Reducing Memory Latency by Improving Resource Utilization

TL;DR: This work attacks a DRAM macro made by Hwang et.

Operating system-level on-chip resource management in the mutlicore era

TL;DR: A hot-page coloring approach that enforces cache partitioning on only a small set of frequently accessed (or hot) pages to segregate most inter- thread cache conflicts is proposed and it is demonstrated that resource-aware scheduling on multicore-based SMP platforms can mitigate resource contention.
Proceedings ArticleDOI

Rethinking Memory System Design

Onur Mutlu
TL;DR: This talk discusses major challenges facing modern memory systems in the presence of greatly increasing demand for data and its fast analysis, and examines some promising research and design directions to overcome these challenges and thus enable scalable memory systems for the future.
Journal ArticleDOI

Large Scale Studies of Memory, Storage, and Network Failures in a Modern Data Center

TL;DR: This dissertation measures and model the device failures in a large scale Internet service company, Facebook, and focuses on three device types that form the foundation of Internet service data center infrastructure: DRAM for main memory, SSDs for persistent storage, and switches and backbone links for network connectivity.
Journal ArticleDOI

CAFFEINE: A Utility-Driven Prefetcher Aggressiveness Engine for Multicores

TL;DR: CAFFEINE is proposed, a model-based approach that analyzes the effectiveness of a prefetcher and uses a metric called net utility to control the aggressiveness, which provides net processor cycles saved because of prefetching by approximating the cycles saved across the memory subsystem, from last-level cache to DRAM.
References
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Proceedings ArticleDOI

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Journal ArticleDOI

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TL;DR: It is demonstrated that performance on a hardware multithreaded processor is sensitive to the set of jobs that are coscheduled by the operating system jobscheduler, and that a small sample of the possible schedules is sufficient to identify a good schedule quickly.
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