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Journal ArticleDOI

Parallelism-Aware Batch Scheduling: Enhancing both Performance and Fairness of Shared DRAM Systems

Onur Mutlu, +1 more
- Vol. 36, Iss: 3, pp 63-74
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TLDR
A parallelism-aware batch scheduler that seamlessly incorporates support for system-level thread priorities and can provide different service levels, including purely opportunistic service, to threads with different priorities, and is also simpler to implement than STFM.
Abstract
In a chip-multiprocessor (CMP) system, the DRAM system isshared among cores. In a shared DRAM system, requests from athread can not only delay requests from other threads by causingbank/bus/row-buffer conflicts but they can also destroy other threads’DRAM-bank-level parallelism. Requests whose latencies would otherwisehave been overlapped could effectively become serialized. As aresult both fairness and system throughput degrade, and some threadscan starve for long time periods.This paper proposes a fundamentally new approach to designinga shared DRAM controller that provides quality of service to threads,while also improving system throughput. Our parallelism-aware batchscheduler (PAR-BS) design is based on two key ideas. First, PARBSprocesses DRAM requests in batches to provide fairness and toavoid starvation of requests. Second, to optimize system throughput,PAR-BS employs a parallelism-aware DRAM scheduling policythat aims to process requests from a thread in parallel in the DRAMbanks, thereby reducing the memory-related stall-time experienced bythe thread. PAR-BS seamlessly incorporates support for system-levelthread priorities and can provide different service levels, includingpurely opportunistic service, to threads with different priorities.We evaluate the design trade-offs involved in PAR-BS and compareit to four previously proposed DRAM scheduler designs on 4-, 8-, and16-core systems. Our evaluations show that, averaged over 100 4-coreworkloads, PAR-BS improves fairness by 1.11X and system throughputby 8.3% compared to the best previous scheduling technique, Stall-Time Fair Memory (STFM) scheduling. Based on simple request prioritizationrules, PAR-BS is also simpler to implement than STFM.

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Citations
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Proceedings ArticleDOI

Memory systems in the many-core era: challenges, opportunities, and solution directions

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DRAMSys4.0: A Fast and Cycle-Accurate SystemC/TLM-Based DRAM Simulator

TL;DR: This paper presents DRAMSys4.0, which is, to the best of the knowledge, the fastest cycle-accurate open-source DRAM simulator and has a large range of functionalities and presents optimization techniques to achieve a high simulation speed while maintaining full temporal accuracy.
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A Quantitative Study of Memory System Interference in Chip Multiprocessor Architectures

TL;DR: The goal in this work is to quantify the latency penalties due to interference in all hardware-controlled, shared units (i.e. the on-chip interconnect, shared cache and memory bus) and to simulate a wide variety of realistic CMP architectures.
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RowClone: Accelerating Data Movement and Initialization Using DRAM.

TL;DR: RowClone significantly reduces the raw latency and energy consumption of bulk data copy and initialization and directly translates to improvement in performance and energy efficiency of systems running copy or initialization-intensive workloads.
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