Pattern-Based Approach to Current Density Verification
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TLDR
Experimental results show the effectiveness of the methodology based on pre-calculation of current density distribution for common layout patterns based on layout patterns common in IC designs.Abstract:
Methodology of static verification of current density based on layout patterns common in IC designs is proposed. The methodology is based on pre-calculation of current density distribution for common layout patterns. Then using the obtained data to calculate current densities of large circuits by partitioning them to selected patterns. Presented experimental results show the effectiveness of the approach.read more
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Journal ArticleDOI
Electromigration in submicron interconnect features of integrated circuits
TL;DR: In this paper, the authors present an overview of EM models from their origins in classical materials science methods up to the most recent developments for submicron interconnect features, as well as the application of ab initio and first principle methods.
Proceedings ArticleDOI
Reliability challenges for advanced copper interconnects: Electromigration and time-dependent dielectric breakdown (TDDB)
TL;DR: In this article, the authors focus on electromigration and time dependent dielectric breakdown (TDDB) in Cu interconnect structures and propose a method to ensure the reliability of the low-k material.
Journal ArticleDOI
Statistical Evaluation of Electromigration Reliability at Chip Level
Baozhen Li,Paul S. McLaughlin,Jeanne P. Bickford,Peter A. Habitz,Dileep N. Netrabile,Timothy D. Sullivan +5 more
TL;DR: In this paper, the relationship between element level and chip level EM failure probability is discussed, and examples of EM evaluation of chip designs are provided to balance the two factors for chip design to achieve the best performance while maintaining chip-level EM reliability.
Proceedings ArticleDOI
Current calculation on VLSI signal interconnects
TL;DR: An efficient static current calculation technique is proposed that can handle the calculation of average, RMS and peak currents in order to perform a comprehensive reliability validation in IC designs and is integrated into a reliability verification flow to be tested on a SoC design.
Proceedings ArticleDOI
Research on failure modes and mechanisms of integrated circuits
TL;DR: In this paper, the authors have summarized the development of research on failure modes of integrated circuits, then different types of failure mechanisms such as electromigration, oxide dielectric breakdown, hot carrier aging were discussed, the corresponding relationship between the failure mode, failure mechanisms and the IC were build here, at last problems on the research were analyzed and suggestions for future investigations were also made.