scispace - formally typeset
Journal ArticleDOI

Pulse Power Failure Modes in Semiconductors

Dante M. Tasca
- 01 Jan 1970 - 
- Vol. 17, Iss: 6, pp 364-372
Reads0
Chats0
TLDR
In this paper, the permanent damage levels associated with a number of different devices and failure mechanisms associated with each were determined both for positive and negative polarity pulses at different conditions of quiescent bias and pulse width.
Abstract
Semiconductor devices operating under both biased and unbiased conditions are vulnerable to permanent damage from relatively moderate levels of pulsed electrical energy, particularly of submicrosecond pulse duration. An experimental study was performed to determine the permanent damage levels associated with a number of different devices and to identify the failure mechanisms associated with each. The device types investigated included general purpose and high speed computer diodes, a medium power diode, medium frequency and UHF transistor amplifiers, and a dielectrically isolated diode gate expander. The permanent damage levels associated with these devices were determined both for positive and negative polarity pulses at different conditions of quiescent bias and pulse width. The pulse duration times included the range of 30 to 300 nanoseconds, and in some instances, up to 1 microsecond. Failure models for both thermal second breakdown induced damage to the semiconductor junction and thermal damage to the device interconnecting leads and metallization patterns were also developed.

read more

Citations
More filters
Book

ESD in silicon integrated circuits

TL;DR: ESD Phenomena and Test Methods The Physics of ESD Protection Circuit Elements Requirements and Synthesis of ESD Protection Circuits Design and Layout Requirements Analysis and Case Studies Modelling of ESC in Integrated Circuits Effects of Processing and Packaging.
Journal ArticleDOI

Thermal failure in semiconductor devices

TL;DR: In this paper, a first principles approach to the problem of thermal breakdown in semiconductor devices is developed using Green's function formalism, which allows all three dimensions of the defect to take on the full range of values.
Journal ArticleDOI

ESD: a pervasive reliability concern for IC technologies

TL;DR: In this article, a review of the ESD phenomena along with the test methods, the appropriate on-chip protection techniques, and the impact of process technology advances from CMOS to BiCMOS on the sensitivity of IC protection circuits are presented.
Journal ArticleDOI

Electrostatic discharge in semiconductor devices: an overview

TL;DR: In this article, the impact of ESD on the IC industry and details the four stages of an ESD event: (1) charge generation, (2) charge transfer, (3) device response and (4) device failure.
Journal ArticleDOI

Characterization and modeling of second breakdown in NMOST's for the extraction of ESD-related process and design parameters

TL;DR: In this article, the effective process and design-related parameters from the high-current I-Vcharacteristics of NMOSTs were determined for use in the development of electrostatic discharge (ESD) protection circuits.
References
More filters
Journal ArticleDOI

Determination of Threshold Failure Levels of Semiconductor Diodes and Transistors Due to Pulse Voltages

TL;DR: In this article, the authors present the results of an extensive experimental program to determine pulse power failure levels of semiconductor junctions, and a semi-empirical formula, based on experimental data and on a simple thermal failure model is given.
Journal ArticleDOI

Current mode second breakdown in epitaxial planar transistors

TL;DR: In this paper, the authors describe a voltage switchback in epitaxial transistors that occurs when the emitter injects at a collector voltage in excess of the collector-emitter sustaining voltage, characterized by delay and voltage fall times on the order of a nanosecond.
Journal ArticleDOI

Thermal breakdown in silicon p-n junction devices

TL;DR: In this paper, current constriction in a p-n junction under a thermal mode of breakdown is analyzed and expressions for terminal voltage and radius of constriction are derived for silicon devices.
Related Papers (5)