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Open AccessJournal ArticleDOI

Shielding Heterogeneous MPSoCs From Untrustworthy 3PIPs Through Security- Driven Task Scheduling

TLDR
This work proposes to incorporate trojan toleration into MPSoC platforms by revising the task scheduling step of theMPSoC design process, and imposes a set of security-driven diversity constraints into the scheduling process, enabling the system to detect the presence of malicious modifications or to mute their effects during application execution.
Abstract
Multiprocessor system-on-chip (MPSoC) platforms face some of the most demanding security concerns, as they process, store, and communicate sensitive information using third-party intellectual property (3PIP) cores. The complexity of MPSoC makes it expensive and time consuming to fully analyze and test during the design stage. This has given rise to the trend of outsourcing design and fabrication of 3PIP components, that may not be trustworthy. To protect MPSoCs against malicious modifications, we impose a set of security-driven diversity constraints into the task scheduling step of the MPSoC design process, enabling the system to detect the presence of malicious modifications or to mute their effects during application execution. We pose the security-constrained MPSoC task scheduling as a multidimensional optimization problem, and propose a set of heuristics to ensure that the introduced security constraints can be fulfilled with a minimum impact on the other design goals such as performance and hardware. Experimental results show that without any extra cores, security constraints can be fulfilled within four vendors and 81% overhead in schedule length.

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Citations
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Journal ArticleDOI

A Multi-Layer Hardware Trojan Protection Framework for IoT Chips

TL;DR: A multi-layer hardware Trojan protection framework for the Internet-of-Things perception layer called RG-Secure, which combines the third-party intellectual property trusted design strategy with the scan-chain netlist feature analysis technology, shows a promising approach to ensure security during the design stage.
Proceedings ArticleDOI

Shielding heterogeneous MPSoCs from untrustworthy 3PIPs through security-driven task scheduling

TL;DR: This work poses the security-constrained MPSoC task scheduling as a multidimensional optimization problem, and proposes a set of heuristics to ensure that the introduced security constraints can be fulfilled with a minimum impact on the other design goals such as performance and hardware.
Proceedings ArticleDOI

A mutual auditing framework to protect IoT against hardware Trojans

TL;DR: The goal is to develop a lightweight framework to monitor communications in the IoT that is able to detect any attempt to leak information or collude with other malicious nodes, thus constructing trustworthy communication channels between untrustworthy nodes.
Journal ArticleDOI

Ten years of hardware Trojans: a survey from the attacker's perspective

TL;DR: The authors attempt to make a review of the hardware Trojan design and implementations in the last decade and also provide an outlook, focusing on the attacker's methods, capabilities, and challenges when the attacker designs and implements a hardware Trojan.
Proceedings ArticleDOI

Self Aware SoC Security to Counteract Delay Inducing Hardware Trojans at Runtime

TL;DR: This work proposes a self aware approach which works on the observe-decide-act (ODA) paradigm to counteract the effects of Trojans, which may induce sudden unintentional delays at runtime, affecting the basic security principles of the SoC.
References
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New methods to color the vertices of a graph

TL;DR: An exact method is given which performs better than the Randall-Brown algorithm and is able to color larger graphs and the new heuristic methods, the classical methods, and the exact method are compared.
Journal ArticleDOI

Static scheduling algorithms for allocating directed task graphs to multiprocessors

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Journal ArticleDOI

A compile-time scheduling heuristic for interconnection-constrained heterogeneous processor architectures

TL;DR: The authors present a compile-time scheduling heuristic called dynamic level scheduling, which accounts for interprocessor communication overhead when mapping precedence-constrained, communicating tasks onto heterogeneous processor architectures with limited or possibly irregular interconnection structures.
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