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Open AccessJournal ArticleDOI

Shielding Heterogeneous MPSoCs From Untrustworthy 3PIPs Through Security- Driven Task Scheduling

TLDR
This work proposes to incorporate trojan toleration into MPSoC platforms by revising the task scheduling step of theMPSoC design process, and imposes a set of security-driven diversity constraints into the scheduling process, enabling the system to detect the presence of malicious modifications or to mute their effects during application execution.
Abstract
Multiprocessor system-on-chip (MPSoC) platforms face some of the most demanding security concerns, as they process, store, and communicate sensitive information using third-party intellectual property (3PIP) cores. The complexity of MPSoC makes it expensive and time consuming to fully analyze and test during the design stage. This has given rise to the trend of outsourcing design and fabrication of 3PIP components, that may not be trustworthy. To protect MPSoCs against malicious modifications, we impose a set of security-driven diversity constraints into the task scheduling step of the MPSoC design process, enabling the system to detect the presence of malicious modifications or to mute their effects during application execution. We pose the security-constrained MPSoC task scheduling as a multidimensional optimization problem, and propose a set of heuristics to ensure that the introduced security constraints can be fulfilled with a minimum impact on the other design goals such as performance and hardware. Experimental results show that without any extra cores, security constraints can be fulfilled within four vendors and 81% overhead in schedule length.

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Citations
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Journal ArticleDOI

Hardware Trojan Mitigation in Pipelined MPSoCs

TL;DR: PMPGuard, a mechanism that detects the presence of hardware Trojans in Third Party Intellectual Property cores of PMPSoCs by continuous monitoring and testing and recovers the system by switching the infected processor core with another one, is presented.
Journal ArticleDOI

Security Measures Against a Rogue Network-on-Chip

TL;DR: It is illustrated that a rogue NoC (rNoC) can selectively disrupt the perceived availability of on-chip resources, thereby causing large performance bottlenecks for the applications running on the MPSoC platform.
Journal ArticleDOI

An Automated Security-Aware Approach for Design of Embedded Systems on MPSoC

TL;DR: This work proposes a security-aware systematic design approach which explores the design space, given a system-level application description, by generating potential architecture configurations of execution platform nodes that are interconnected using a NoC.
Posted Content

An Interposer-Based Root of Trust: Seize the Opportunity for Secure System-Level Integration of Untrusted Chiplets

TL;DR: This work advocates the integration of untrusted commodity components/chiplets with physically separate, entrusted logic components that provides a modern root of trust for secure system-level integration through 2.5D interposer technology.
Journal ArticleDOI

Criticality based reliability against hardware Trojan attacks for processing of tasks on reconfigurable hardware

TL;DR: This work initially explores how HTHs implanted by 3PIP vendors in the bitstreams may cause active attacks, and develops strategies to ensure reliability for processing of mixed critical tasks on reconfigurable hardware against HTH attacks.
References
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New methods to color the vertices of a graph

TL;DR: An exact method is given which performs better than the Randall-Brown algorithm and is able to color larger graphs and the new heuristic methods, the classical methods, and the exact method are compared.
Journal ArticleDOI

Static scheduling algorithms for allocating directed task graphs to multiprocessors

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Journal ArticleDOI

A compile-time scheduling heuristic for interconnection-constrained heterogeneous processor architectures

TL;DR: The authors present a compile-time scheduling heuristic called dynamic level scheduling, which accounts for interprocessor communication overhead when mapping precedence-constrained, communicating tasks onto heterogeneous processor architectures with limited or possibly irregular interconnection structures.
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