Journal ArticleDOI
Standby supply voltage minimization for deep sub-micron SRAM
TLDR
In this article, the DRV of a standard low leakage SRAM module is modeled as a function of process and design parameters, and analyzes the SRAM cell stability when VDD approaches DRV.About:
This article is published in Microelectronics Journal.The article was published on 2005-09-01. It has received 61 citations till now. The article focuses on the topics: Static random-access memory.read more
Citations
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Journal ArticleDOI
Ultralow-voltage, minimum-energy CMOS
Scott Hanson,Bo Zhai,Kerry Bernstein,David Blaauw,A. Bryant,Leland Chang,K. K. Das,Wilfried Haensch,E. J. Nowak,Dennis Sylvester +9 more
TL;DR: This work reviews circuit behavior at low voltages, specifically in the subthreshold (Vdd < Vth) regime, and suggests new strategies for energy-efficient design, and discusses the energy benefits of techniques such as multiple-threshold CMOS and adaptive body biasing.
Proceedings ArticleDOI
Analyzing static noise margin for sub-threshold SRAM in 65nm CMOS
TL;DR: This paper evaluates the static noise margin (SNM) of 6T SRAM bitcells operating in sub-threshold and analyses the statistical distribution of SNM with process variation and provides a model for the tail of the PDF that dominates SNM failures.
Journal ArticleDOI
Technologies for Ultradynamic Voltage Scaling
Anantha P. Chandrakasan,Denis C. Daly,D.F. Finchelstein,Joyce Kwong,Yogesh Ramadass,Mahmut E. Sinangil,Vivienne Sze,Naveen Verma +7 more
TL;DR: Voltage-scalable circuits such as logic cells, SRAMs, ADCs,ADCs, and dc-dc converters are presented, using these circuits as building blocks for two different applications.
Proceedings ArticleDOI
Statistical modeling for the minimum standby supply voltage of a full SRAM array
TL;DR: Two fast and accurate methods to estimate the lower bound of supply voltage scaling for standby SRAM/cache leakage power reduction of an SRAM array and a new statistical model based on the connection between DRV and static noise margin are presented.
Journal ArticleDOI
Ultra-low-power design
Jan M. Rabaey,J. Ammer,Brian Otis,F. Burghardt,Y.H. Chee,Nathan Pletcher,Michael D. Sheets,Huifang Qin +7 more
TL;DR: In this article, the authors describe how such an integrated approach has indeed made it possible to produce a PicoNode that meets the original goals, which combines innovative technologies, such as radiofrequency microelectromechanical systems (RF-MEMS) with ultra-low-power RF and digital integrated circuit (IC) design, and employs aggressive energy-scavenging and packaging techniques.
References
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Book
Digital integrated circuits: a design perspective
TL;DR: In this paper, the authors present a survey of the state-of-the-art in the field of digital integrated circuits, focusing on the following: 1. A Historical Perspective. 2. A CIRCUIT PERSPECTIVE.
Journal ArticleDOI
Static-noise margin analysis of MOS SRAM cells
TL;DR: In this article, the stability of both resistor-load (R-load) and full-CMOS SRAM cells is investigated analytically as well as by simulation, and explicit analytic expressions for the static-noise margin (SNM) as a function of device parameters and supply voltage are derived.
Journal ArticleDOI
Design challenges of technology scaling
TL;DR: In this article, the authors look closely at past trends in technology scaling and how well microprocessor technology and products have met these goals and project the challenges that lie ahead if these trends continue.
Proceedings ArticleDOI
Cache decay: exploiting generational behavior to reduce cache leakage power
TL;DR: This paper discusses policies and implementations for reducing cache leakage by invalidating and “turning off” cache lines when they hold data not likely to be reused, and proposes adaptive policies that effectively reduce LI cache leakage energy by 5x for the SPEC2000 with only negligible degradations in performance.