Technologies for Ultradynamic Voltage Scaling
Anantha P. Chandrakasan,Denis C. Daly,D.F. Finchelstein,Joyce Kwong,Yogesh Ramadass,Mahmut E. Sinangil,Vivienne Sze,Naveen Verma +7 more
- Vol. 98, Iss: 2, pp 191-214
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TLDR
Voltage-scalable circuits such as logic cells, SRAMs, ADCs,ADCs, and dc-dc converters are presented, using these circuits as building blocks for two different applications.Abstract:
Energy efficiency of electronic circuits is a critical concern in a wide range of applications from mobile multi-media to biomedical monitoring. An added challenge is that many of these applications have dynamic workloads. To reduce the energy consumption under these variable computation requirements, the underlying circuits must function efficiently over a wide range of supply voltages. This paper presents voltage-scalable circuits such as logic cells, SRAMs, ADCs, and dc-dc converters. Using these circuits as building blocks, two different applications are highlighted. First, we describe an H.264/AVC video decoder that efficiently scales between QCIF and 1080p resolutions, using a supply voltage varying from 0.5 V to 0.85 V. Second, we describe a 0.3 V 16-bit micro-controller with on-chip SRAM, where the supply voltage is generated efficiently by an integrated dc-dc converter.read more
Citations
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Ultra-Low Power VLSI Circuit Design Demystified and Explained: A Tutorial
TL;DR: It is shown that many paradigms and approaches borrowed from traditional above-threshold low-power VLSI design are actually incorrect and common misconceptions in the ULP domain are debunked and replaced with technically sound explanations.
Proceedings ArticleDOI
Power-Aware Speed Scaling in Processor Sharing Systems
TL;DR: Study of how to optimally scale speed to balance mean response time and mean energy consumption under processor sharing scheduling shows that a simple scheme that halts when the system is idle and uses a static rate while the system are busy provides nearly the same performance as the optimal dynamic speed scaling scheme.
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Design, Optimization, and Scaling of MEM Relays for Ultra-Low-Power Digital Logic
TL;DR: In this paper, a sensitivity-based energy-delay optimization approach is developed in order to establish simple relay design guidelines, and it is found that, at the optimal design point, every 2 X energy increase can be traded off for a ~1.5x reduction in relay delay.
Journal ArticleDOI
Power-aware speed scaling in processor sharing systems: Optimality and robustness
TL;DR: This paper studies the optimal way to scale speed to balance response time and energy consumption under processor sharing scheduling and shows that using a static rate while the system is busy provides nearly optimal performance, but having a wider range of available speeds increases robustness to different traffic loads.
Proceedings ArticleDOI
Booster: Reactive core acceleration for mitigating the effects of process variation and application imbalance in low-voltage chips
TL;DR: This paper presents Booster, a simple, low-overhead framework for dynamically rebalancing performance heterogeneity caused by process variation and application imbalance, and presents two implementations of Booster: Booster VAR, which virtually eliminates the effects of core-to-core frequency variation in near-threshold CMPs, and Booster SYNC, which additionally reduces the effect of imbalance in multithreaded applications.
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