538
IEEE Transactions on Power Delivery,
Vol.
13,
No.
2,
April
1998
Statcom Controls for Operation with Unbalanced Voltages
Clark
Hochgraf Robert
H.
Lasseter
Student Member Fellow
Electrical and Computer Engineering Department
University of Wisconsin-Madison, Madison, WI
53706
Abstract-Voltage Sourced Static Var
Figure
1
shows a single phase equivalent of the Statcom. A
Compensators such as the Statcom need to be able
voltage source inverter produces a set of three phase voltages,
to handle unbalanced voltages. Mild imbalance can
Vc, that are in phase with the system voltage, Vs. A small
be caused by unbalanced loads while severe short-
reactance, Xc, is used to link the compensator voltage to the
term imbalance can be caused by power system
power system. When Vc>Vs, a reactive current, ic, is produced
faults. A synchronous frame voltage regulator is
that leads
Vs
and when Vc<Vs, the current lags Vs.
presented that works even when three phase
The Statcom can be used to improve the quality of power
symmetry is lost. This regulator addresses voltage
provided to industrial and commercial consumers by reducing
imbalance by using separate regulation loops for
the positive and negative sequence components
of
the voltage. The proposed regulator allows the
Effect
of
Unbalanced Voltages
Statcom to ride through severe transient imbalance
without disconnecting from the power system and,
One problem that the Statcom must deal with in the
further, to assist in rebalancing voltages he
distribution system is voltage imbalance. Steady-state voltage
regulator maintains sufficient bandwidt to
imbalance can arise from unequal loading on each phase
or
perform flicker compensation. The controller's
from unbalanced faults on the power system, which cause
performance is simulated for a Statcom in a model
single phase voltage sags. These sags can range from mild to
distribution system where it is subjected to a
severe depending on the distance to the fault.
severe single line to ground fault and a rapidly
Voltage imbalance can be quantified using the following
varying three phase load.
Keywords: Statcom, Inverter, Static Var
voltage flicker and correcting small voltage sags.
definition
[5]:
(1)
Compensation, synchronous reference frame,
v&V
unbalance, imbalance.
%
Imbalance
=
100
X-
17
I.
INTRODUCTION
Static var compensation can be utilized to regulate voltage,
control power factor, and stabilize power flow
[l].
Most var
compensators employ a combination of fixed or switched
capacitance and thyristor controlled reactance. Static var
compensators based on a voltage sourced inverter, known
as
Statcoms, have been proposed and demonstrated
[2-41
in an
effort to further improve performance, decrease size,
and
increase flexibility.
PE-002-PWF!D-0-07-1997 A paper recommended
the IEEE Transmission and Distribution Committee
of
the
IEEE
Power
Engineering Society for publication in the IEEE Transactions
on
Power
Delivery. Manuscript submitted January 14, 1997; made available for
printing August 19, 1997.
"
avg
where Vdev is the maximum voltage deviation from the
average and Vavg is the average voltage.
Excessive imbalance is detrimental
as
it causes heating in
motors requiring them to be derated. For example, with
5%
imbalance, the motor derating factor is
0.76.
Imbalance can
also affect sensitive single phase loads because it creates
undervoltages on one or more of the lines.
Voltage imbalance
also
causes
a
problem for the Statcom.
As
shown in figure
1,
the Statcom
looks
like a voltage source
behind
a
small transient reactance. When the system voltage,
Vs, is unbalanced, negative sequence currents can flow into
the compensator limited only by the Statcom reactance, Xc.
I
I
V
Power
vc
xc
-+$pi+"?
+
sm
System
StatCom
Figure
1.
Statcom single phase equivalent model.
Prior Statcom work has indicated the existence of
problems caused by imbalance.
In
[3], severe imbalance forces
the Statcom converter into standby mode, where GTO firing is
blocked. This is done to prevent excessive ripple current in the
0885-8977/98/$10.00
0
1997
IEEE
539
separately representing either the positive or negative sequence
circuit. This assumption is helpful in simplifying the
problem, though it is not strictly true for many conceivable
situations, such as when
Zs
is not equal in all three phases.
Nonetheless, the compensator voltage may be synthesized
using only a measurement of the regulated bus voltage.
Consider the case for the negative sequence component of the
compensator voltage. Setting the compensator voltage, Vi
equal to k times the regulated bus voltage, Vi
,
results in the
dc
bus capacitor. As a result, the converter is off-line
and
provides
no voltage support for lOOms after the imbalance is
removed.
In
[4],
an analysis of the effect of imbalance on Statcom
currents is presented. The analysis assumes that a multi-pulse
inverter is used where the inverter modulation index (mi
=vfldc) is fixed. The magnitude of the voltage is varied by
changing the
dc
bus voltage. The results of this analysis
are
used to size the inverter's dc bus capacitor to avoid resonance
whenever unbalanced voltages are present. Even with
a
carefully sized capacitor, the compensator still
experiences
uncontrolled negative sequence currents.
II.
CONTROLS FOR HANDLING IMBALANCE
To deal with the issue of imbalance, a Statcom voltage
regulator built upon sequence component theory is described.
The controller unbalances the compensator voltages in
response to the imbalance on the distribution system. By
doing this, two benefits can be realized. First, negative
sequence current flow into the Statcom can be controlled.
Second, the Statcom can be used to rebalance the system
voltage regardless
of
the source of imbalance.
In
[3-41,
the generation of negative sequence in the
inverter's voltage is not examined because of the constraints
on modulation inherent in the multi-pulse converters used. The
inverters could not produce unequal voltages on each phase leg.
However, by using a pulse-width-modulation or multi-level
[7]
type inverter, the fixed modulation index constraint is removed
and more advanced control can be applied.
Formulation
of
the Unbalanced Voltage Regulation
Problem
The proposed voltage regulator separates the voltage
regulation into two parallel problems: Regulating the positive
sequence component of the voltage and the negative sequence
component of the voltage. Using the separate loops, the
negative sequence component can be driven towards zero while
the positive sequence component can be driven towards its
desired value.
V
S
Z
1
Figure
2.
Reduced model for regulator circuit.
Figure
2
shows a simplified single phase model of the
compensator in a distribution system. The power system
Thevenin voltage
is
Vs
and the Thevenin impedance is
Zs.
The
Statcom's voltage
is
Vc and the Statcom reactance is Xc.
The
aggregate
load
impedance
is
Z1.
Assuming
that
the sequence
components are not coupled, figure
2
can be thought
of
as
negative sequence component of the
being
regulated bus voltage
As
the feedback gain, k,
goes to infinity, the negative
sequence component
of the regulated bus voltage, Vi
,
goes
to zero.
111.
SYNCHRONOUS FRAME TRANSFORM FOR
UNBALANCEDCONDITIONS
To achieve the infinite feedback gain value
required for
elimination of the negative sequence component as in
(2),
the
regulation should be performed
in the synchronous reference
frame. In the synchronous frame, the regulated quantities
appear as dc rather than as
6OHz
ac. Because the regulated
quantities are dc, integral gain can be used to increase the
effective value of k to infinity in the steady-state, giving
perfect command tracking.
The traditional synchronous frame transform
[6]
can be used
to indicate the positive sequence component
of voltage.
However, it has problems when the phase voltages
are
unbalanced. The transform produces an output that contains a
second harmonic component in addition to a dc component.
The positive sequence component is
no
longer clearly indicated
because of the loss
of
three phase symmetry in the input
quantities.
Lhc::
120Hz 180Hz
120Hz 180Hz
2
cos(8)
-2
sin(8)
Figure 3. Single phase synchronous frame transformation and
filtering
To eliminate the
need
for three phase symmetry, a new
single phase synchronous frame transform is introduced. The
transform projects each phase voltage onto an orthogonal
frame
phase voltages are combined to obtain the sequence
synohronous
reference
frame
and
then
later,
the
synchronous
540
components. The block diagram of the synchronous frame
transformation is shown in figure 3 and the detailed equations
of transformation are presented in appendix
A.
The advantage of the modified transform is that it can
be
used during balanced or unbalanced conditions, without
modification.
Also,
the sequence components are easily found
by algebraic manipulation of the synchronous frame phase
voltages.
The synchronous frame transformation in figure 3 consists
of heterodyning the time domain phase voltage with -2 sin(8)
and 2 cos(@) to produce dc plus a second harmonic. The second
harmonic is filtered out to reveal the projection of the voltage
onto the synchronous reference frame.
The new transform, however, suffers from an additional
delay imposed by its requirement for filtering of the second
harmonic. The step response of the second harmonic notch
filter plus low pass filter of figure
3
determines the bandwidth
of the transformation.
Step Response
of
Notch
+
LP
Filter
s
1-
8
5
0.8
0.6
Dc
Q
S
0.4
(I)
I
1.21
~__
,
.
.
-
0.2
y
0’
I
0
0.005
0.01
0.01
5
Time (sec)
Figure
4.
Step response of cascaded notch and low pass filter.
Figure
4
shows the step response of the overall notch plus
low pass filter. The oscillatory response seen at 0.002ms is
caused by the notch filter. The damping of this must be
traded
off versus the notch depth. The filter requires about 7ms for its
transient response to settle. As a result, the regulator using
this filter can’t be expected to respond in less than half an
ac
cycle. However, half-cycle response is adequately fast for
attenuating voltage flicker.
IV. SEQUENCE COMPONENT REGULATOR
Using the new transform, a synchronous frame voltage
regulator is developed as shown in figure
5.
The regulator
measures the
bus
voltage and separates it into its positive
and
negative sequence components. For each sequence component,
separate regulation loops are applied to the magnitude and the
phase angle. Identical loops are used for the positive
and
negative sequence components.
Below the main regulator loop in figure
5,
two additional
control loops are shown, one for dc bus voltage regulation
and
one for balancing of capacitor voltages in the multi-level
inverter.
A. Magnitude Regulator
The sequence magnitude is compared to its commanded
reference value producing an error signal, which is fed into a
proportional-integral-derivative controller. The output of the
PID control is a signal corresponding to the voltage drop
across the Statcom reactance, Xc. By limiting the value of this
voltage drop, the inverter current is limited. The voltage drop
across the reactance is then
added
to magnitude of the system
voltage to create the command for the inverter voltage
magnitude.
B.
Angle Regulator
The angle of the inverter positive sequence voltage is used
to control the inverter’s total
dc
bus voltage. The
dc
bus
voltage regulator consists of a PI loop, which generates a
power reference signal. The power reference signal is then
compared with the actual positive sequence power and the error
fed to a proportional gain regulator with limits. The output
is
the difference in angle between the measured system voltage
positive sequence angle and the inverter’s angle. The difference
angle is then
ssdded
to angle of the system voltage to get the
inverter’s angle.
Since the positive sequence angle is used to control the
dc
bus voltage, the negative sequence angle is free for any special
purpose.
In
the multi-level inverter, the negative sequence
power is used to help control individual dc bus capacitor
voltages.
If
the multi-level inverter is not used, the negative
sequence power can be set to zero.
When the five-level inverter is used, the voltages of the
inner capacitors, C2 and C3, are compared
to
that of the outer
capacitors, C1 and C4. A PI control loop generates a negative
sequence power command based on the difference between these
voltages. Without this loop, the capacitor voltages can become
unequal when the compensator is producing negative sequence
current.
With the magnitudes and angles of inverter sequence
voltages determined, these values are transformed back to phase
quantities and summed to create the total inverter voltage
command. The multi-level inverter receives these commands
and uses a harmonically optimized lookup table to create
gating signals which synthesize the desired fundamental
component voltages.
V. SIMULATION MODEL
The
operation
of
the
regulator
is
simulated
in
a
distribution
level Statcom using the Electromagnetic Transients Program.
Figure
6
shows the one line diagram of the distribution
system, which includes resistive-inductive loads, adjustable
speed drives, and a large induction motor.
The distribution system model
is
based on the work in
[SI
with reference to
[9-IO].
Table
I1
gives the distribution system
541
vd' vq'
v-
v-
dq
Figure
5.
Statcom voltage regulator using separate regulation loops for positive and negative sequence components. The dc bus
voltage regulator and the multi-level inverter capacitor voltage sharing loops are shown separately, below the main loop.
model parameters. Note that the transformer per unit
impedances
are
given
on
the transformer's power base.
The
B.
Simulated Events
adjustable speed drives are modeled as six pulse diode rectifiers
loaded by a dc bus capacitor and load resistor.
A.
Statcom Model
The Statcom is connected at bus
4
in figure
6.
A five-level
inverter is used for the Statcom with ratings given in Table
I.
It
should
be noted that the compensator's
MVA
rating is
chosen to be fairly large in order to give a substantial range of
voltage control.
The inverter uses fundamental frequency switching but due
to its step-like output voltage waveform, it is possible to
reduce a few low-order harmonics.
A
switching angle lookup
table is used, which minimizes 5th and 7th harmonics over a
wide range of modulation indices.
No
dc
side energy source is
used but the dc bus capacitor is large. The
dc
bus voltage is
held at a fixed value while the modulation index is varied to
control fundamental voltage. The operation of the multi-level
inverter
is
described
in
greater
detail in
[6].
The regulator's performance
is
shown in response to two
conditions. The first condition is a single phase fault, which
shows the compensator's compatibility with imbalance
and
ability to reduce imbalance. The fault consists
of
a low
impedance to ground placed on phase
A
of line
4.
The second condition is a three phase
load
variation at
5
Hz. This is used to show that the regulator maintains
adequate
bandwidth for flicker reduction even with the transform filter
delays. The load variation is introduced by putting a
squarewave pulsating load torque on the shaft of motor
M1
on
bus
4.
VI.
RESULTS
A.
Single
Phase Fault
The phase A voltage magnitude at substation bus
2
is
reduced to
50%
when the single line
to
ground fault is applied
542
230kv
@
Transmission Equivalent
3
StatCom
T2&
$
480V
4160V
1
Figure
6.
Distribution system model for simulations.
at precisely
0.2
seconds.
During the fault, the compensator
remains within its current limit as shown in figure
7,
while
actively supporting and rebalancing the voltages. The fault
clears at precisely
0.3
seconds. Figure
8
shows the magnitude
of
the positive and negative sequence components
of
the
voltage. When the compensator is active, the magnitude
of
the
negative sequence is reduced and the positive sequence is
increased, subject
to
the current limit of the converter. The
percent imbalance goes from
17.7%
without the compensator
down to
9.3%
with the compensator. Long term imbalance
such as arising from an unbalanced load can be corrected
as
well.
Compen. Currents
w/
SLG
fault on
A
1.5
-1.5
'
I
0.1
0.15
0.2
0.25
0.3
0.35
Time
[SI
Figure
7.
Statcom compensator currents during severe transient
imbalance due
to SLG fault. The fault is present during the
interval from
0.2
seconds to
0.3
seconds.
TABLE
I.
BASE QUANTITIES AND COMPENSATOR
RATINGS
Zbase
Pbase
abase
11.62
Q
15 MVA
377 radls
MVA Rating
1.5
pu
IL
TABLE
II.
DISTRIBUTION SYSTEM MODEL DATA
Line
#
L1
L2
L3
L4
L5
L6
Type
overhead
overhead
overhead
overhead
cable
___
Trfmr#
I
Type
I
Rating
T1
I
A-Y
I15MVA
T2
T3
T4
T5
A-Y
1.5 MVA
1@ L-L
10 kVA
Y-Y
2.5 MVA
Y-Y
5
MVA
P2
RL
1.5 MW, 0.9
pf
P3 R
0.5
MW, 1.0
pf
P4
RL,
1.5 MW,
0.9
pf
P5 R
1.5 MW, 1.0
pf
M1
Ind.
Motor 1200
Hp
Impedance (pu)
0.00016
+
j
0.001
0.0228
+
j'O.0847
0.0290
+
j
0.045
0.0142
+
j 0.16178
0.0145
+
j 0.0225
0.031
+
j 0.031
Impedance (pu)
0.00765
+
j
0.0765
0.006
+
j
0.06
0.002
+
j
0.02
0.0055
+
j
0.055
0.006
+
j
0.06
Inertia
=
15 kg
mA2
IV+I, IV-l
Phase
A
Sagged
50%
0.8
w/o
Comp.
"
0.1
0.2
0.3
0.4
Time
[SI
Figure
8.
Magnitude of positive and negative sequence
components during single line to
ground
fault
with
and
without Statcom.
B.
Three Phase Load Variation
Figure
9
shows the variation in the three phase voltage
when the load
on motor M1
is
varying at
5
Hz.
During the
load variation, the rms voltage at bus
4
varies by
2%
without
the compensator vs. less than
0.5
% with compensator.