Statistical optimization for process parameters to reduce variability of 32 nm PMOS transistor threshold voltage
H. A. Elgomati,Burhanuddin Yeop Majlis,Ibrahim Ahmad,Fauziyah Salehuddin,Fazrena Azlee Hamid,Azami Zaharim,T. Z. Mohamad,Prakash R. Apte +7 more
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TLDR
In this paper, the effect of process parameters on the threshold voltage of a 32 nm PMOS device was analyzed using Taguchi's method, and the results showed that the VTH was well within ITRS prediction for a 32nm PMOS transistor.Abstract:
This paper explains our investigation of the effect on 32 nm PMOS device threshold voltage (VTH) by four process parameters, namely HALO implantation, Source/Drain (S/D) implantation dose, compensation implantations, and silicide annealing time Taguchi method determines the setting of process parameters in experimental design while analysis of variance (ANOVA) determines the influence of the main process parameters on threshold voltage The fabrication processes of the transistor were performed by ATHENA fabrication simulator, while the electrical characterization of the device was done by an ATLAS characterization simulator These two simulators were combined and the results were analyzed by Taguchi’s method in order to aid in design and optimizing process parameters Threshold voltage (Vth) results were used as the evaluation parameters The results show that the VTH value of –010319 V is achieved for a 32 nm PMOS transistor In conclusion, by utilizing Taguchi’s method to analyze the effect of process parameters, we can adjust threshold voltage (VTH) for PMOS to a stable value of –010319 V that is wellwithin ITRS prediction for a 32 nm PMOS transistor
Key words: 32 nm PMOS device, HALO, compensation implantation, S/D implantation,threshold voltage, Taguchi’s methodread more
Citations
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Proceedings ArticleDOI
Modelling of Process Parameters for 32nm PMOS Transistor Using Taguchi Method
TL;DR: This paper investigates the effect of seven process parameters and two process noise parameters on threshold voltage (Vth) in a 32nm PMOS transistor and finds that the Vth values had the least variance and the mean value could be adjusted to -0.103V +-0.003 for PMOS, which is well within ITRS specifications.
Proceedings ArticleDOI
Scaling down of the 32 nm to 22 nm gate length NMOS transistor
A. H. Afifah Maheran,P. S. Menon,Ibrahim Ahmad,H. A. Elgomati,Burhanuddin Yeop Majlis,Fauziyah Salehuddin +5 more
TL;DR: In this article, the authors provide the downscaling design and simulation of NMOS transistor with 22 nm gate length, based on the 32 nm design simulation from their previous research, and the simulation shows that the optimal value of threshold voltage (V th ) and leakage currents (I on and I off ) was achieved according to specification in ITRS 2011.
Patent
Overvoltage protection for a fine grained negative wordline scheme
Harold Pilo,Richard S. Wu +1 more
TL;DR: In this article, a fine grained negative wordline scheme for SRAM memories was proposed, which includes a circuit having a static random access memory (SRAM) cell including at least a wordline coupled to a plurality of NFETs of a transistor array.
Journal ArticleDOI
Comparative Analysis of Process Parameter Variations in DGFinFET Device Using Statistical Methods
Ameer F. Roslan,Fauziyah Salehuddin,Anis Suhaila Mohd Zain,Norhisham Mansor,K.E. Kaharudin,Ibrahim Ahmad,Haroon Hazura,Abdul Razak Hanim,S. K. Idris,A. M. Zaiton,B. Z. Zarina,Najmiah Radiah Mohamad,Afifah Maheran A. Hamid +12 more
Book ChapterDOI
Comparisons in L32 2k-Factorial and L25 Taguchi for the 16 nm FinFET Statistical Optimization Applications
Ameer F. Roslan,Fauziyah Salehuddin,Anis Suhaila Mohd Zain,K.E. Kaharudin,Abdul Razak Hanim,Haroon Hazura,S. K. Idris +6 more
TL;DR: In this article, the authors examined and analyzed the process parameter variance towards on-state drive current (ION) and leakage current (IOFF) towards the 16 nm double-gate FinFET (DG-FinFET) device by the implementation of 2k-factorial design, with comparisons made against an L25 Taguchi statistical method.
References
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Book
Designing for Quality: An introduction to the best of Taguchi and Western methods of statistical experimental design
TL;DR: The Taguchi approach to quality two-level experiments - full factorial designs two- level experiments - fractional orthogonal designs evaluating variability Taguchi inner and outer arrays experimental designs for factors at three and four levels analysis of variance in engineering design computer software for experimental design using experiments to improve processes.
Journal ArticleDOI
Die casting process optimization using Taguchi methods
TL;DR: In this paper, various significant process parameters of the die casting method of AlSi9Cu13 aluminum alloy have been analyzed and an attempt has been made to obtain optimal settings of die casting parameters, in order to yield the optimum casting density.
Journal ArticleDOI
Process parameter selection for strontium ferrite sintered magnets using Taguchi L9 orthogonal design
TL;DR: In this paper, the selection of process parameters for obtaining optimal magnetic properties in strontium ferrite sintered magnets is discussed, and the Taguchi L9 design is adopted.
Proceedings ArticleDOI
Impact of Layout on 90nm CMOS Process Parameter Fluctuations
Liang-Teck Pang,Borivoje Nikolic +1 more
TL;DR: A test chip has been built to study the effects of layout on the delay and leakage of digital circuits in 90nm CMOS through the spread of ring oscillator frequencies and the transistor leakage is measured using an on-chip ADC.
Proceedings ArticleDOI
Challenges and Opportunities for High Performance 32 nm CMOS Technology
Jeffrey W. Sleight,Isaac Lauer,Omer H. Dokumaci,David M. Fried,Dechao Guo,Bala S. Haran,Shreesh Narasimha,Christopher D. Sheraw,D.V. Singh,Michael D. Steigerwalt,Xinhui Wang,Philip J. Oldiges,D. K. Sadana,Chun-Yung Sung,Wilfried Haensch,Mukesh Khare +15 more
TL;DR: In this article, the impact of pitch and increased parasitics on device performance in the 32 nm node was analyzed and an optimized layout using a relaxed pitch approach was demonstrated to show up to a 15% improvement over conventional layout in ring oscillators.