An object is to provide a semiconductor device of which a manufacturing process is not complicated and by which cost can be suppressed, by forming a thin film transistor using an oxide semiconductor film typified by zinc oxide, and a manufacturing method thereof. For the semiconductor device, a gate electrode is formed over a substrate; a gate insulating film is formed covering the gate electrode; an oxide semiconductor film is formed over the gate insulating film; and a first conductive film and a second conductive film are formed over the oxide semiconductor film. The oxide semiconductor film has at least a crystallized region in a channel region.

Semiconductor device, and manufacturing method thereof

Emerging challenges and materials for thermal management of electronics

Understanding energy dissipation and transport in nanoscale structures is of great importance for the design of energy-efficient circuits and energy-conversion systems. This is also a rich domain for fundamental discoveries at the intersection of electron, lattice (phonon), and optical (photon) interactions. This review presents recent progress in understanding and manipulation of energy dissipation and transport in nanoscale solid-state structures. First, the landscape of power usage from nanoscale transistors (∼10−8 W) to massive data centers (∼109 W) is surveyed. Then, focus is given to energy dissipation in nanoscale circuits, silicon transistors, carbon nanostructures, and semiconductor nanowires. Concepts of steady-state and transient thermal transport are also reviewed in the context of nanoscale devices with sub-nanosecond switching times. Finally, recent directions regarding energy transport are reviewed, including electrical and thermal conductivity of nanostructures, thermal rectification, and the role of ubiquitous material interfaces. 
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Energy dissipation and transport in nanoscale devices

FinFETs and Other Multi-Gate Transistors provides a comprehensive description of the physics, technology and circuit applications of multigate field-effect transistors (FETs). It explains the physics and properties of these devices, how they are fabricated and how circuit designers can use them to improve the performances of integrated circuits. The International Technology Roadmap for Semiconductors (ITRS) recognizes the importance of these devices and places them in the "Advanced non-classical CMOS devices" category. Of all the existing multigate devices, the FinFET is the most widely known. FinFETs and Other Multi-Gate Transistors is dedicated to the different facets of multigate FET technology and is written by leading experts in the field.

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FinFETs and Other Multi-Gate Transistors

Understanding energy dissipation and transport in nanoscale structures is of great importance for the design of energy-efficient circuits and energy-conversion systems. This is also a rich domain for fundamental discoveries at the intersection of electron, lattice (phonon), and optical (photon) interactions. This review presents recent progress in understanding and manipulation of energy dissipation and transport in nanoscale solid-state structures. First, the landscape of power usage from nanoscale transistors (~10^-8 W) to massive data centers (~10^9 W) is surveyed. Then, focus is given to energy dissipation in nanoscale circuits, silicon transistors, carbon nanostructures, and semiconductor nanowires. Concepts of steady-state and transient thermal transport are also reviewed in the context of nanoscale devices with sub-nanosecond switching times. Finally, recent directions regarding energy transport are reviewed, including electrical and thermal conductivity of nanostructures, thermal rectification, and the role of ubiquitous material interfaces.

/pdf/energy-dissipation-and-transport-in-nanoscale-devices-17sw2ubrhz.pdf

Energy Dissipation and Transport in Nanoscale Devices

To a large extent, scaling was not seriously challenged in the past. However, a closer look reveals that early signs of scaling limits were seen in high-performance devices in recent technology nodes. To obtain the projected performance gain of 30% per generation, device designers have been forced to relax the device subthreshold leakage continuously from one to several nA/µm for the 250-nm node to hundreds of nA/µm for the 65-nm node. Consequently, passive power density is now a significant portion of the power budget of a high-speed microprocessor. In this paper we discuss device and material options to improve device performance when conventional scaling is power-constrained. These options can be separated into three categories: improved short-channel behavior, improved current drive, and improved switching behavior. In the first category fall advanced dielectrics and multi-gate devices. The second category comprises mobility-enhancing measures through stress and substrate material alternatives. The third category focuses mainly on scaling of SOI body thickness to reduce capacitance. We do not provide details of the fabrication of these different device options or the manufacturing challenges that must be met. Rather, we discuss the fundamental scaling issues related to the various device options. We conclude with a brief discussion of the ultimate FET close to the fundamental silicon device limit.

Silicon CMOS devices beyond scaling

A 300-mm wafer-level three-dimensional integration (3DI) process using tungsten (W) through-silicon vias (TSVs) and hybrid Cu/adhesive wafer bonding is demonstrated The W TSVs have fine pitch (5 mum), small critical dimension (15 mum), and high aspect ratio (17:1) A hybrid Cu/adhesive bonding approach, also called transfer-join (TJ) method, is used to interconnect the TSVs to a Cu BEOL in a bottom wafer The process also features thinning of the top wafer to 20 mum and a Cu backside BEOL on the thinned top wafer The electrical and physical properties of the TSVs and bonded interconnect are presented and show RLC values that satisfy both the power delivery and high-speed signaling requirements for high-performance 3D systems

A 300-mm wafer-level three-dimensional integration scheme using tungsten through-silicon via and hybrid Cu-adhesive bonding

A method including forming a deep trench in a semiconductor-on-insulator substrate including an SOI layer directly on top of a buried oxide layer directly on top of a base substrate, masking only a top surface of the SOI layer and a sidewall of the SOI layer exposed within an upper portion of the deep trench with a dielectric material without masking any surface of the base substrate exposed within a lower portion of the deep trench, and forming a bottle shaped trench by etching the base substrate exposed in the lower portion of the deep trench selective to the dielectric material and the buried oxide layer.

Wet bottling process for small diameter deep trench capacitors

A method of fabricating and a structure of a merged multi-fin finFET. The method includes forming single-crystal silicon fins from the silicon layer of an SOI substrate having a very thin buried oxide layer and merging the end regions of the fins by growing vertical epitaxial silicon from the substrate and horizontal epitaxial silicon from ends of the fins such that vertical epitaxial silicon growth predominates.

finFETs and methods of making same

FinFET devices are demonstrated with multiple fins (>2) at a 120nm pitch using e-beam lithography to address some key challenges of FINFETs for 32nm node technologies and beyond. Target Vt's are achieved by proper halo design using 20nm fins. Vt scatter due to Fin width variation is greatly reduced with a reduced halo. When such a realistic fin pitch is used, S/D contact formation becomes a serious challenge due to poly-to-active overlay requirements and the need for raised S/D for series resistance reduction. A new FinFET design without S/D contact pads is thus proposed and a selective epitaxial process to merge individual fins is developed

Xinhui Wang

Papers

Silicon CMOS devices beyond scaling

A 300-mm wafer-level three-dimensional integration scheme using tungsten through-silicon via and hybrid Cu-adhesive bonding

Wet bottling process for small diameter deep trench capacitors

finFETs and methods of making same

Investigation of FinFET Devices for 32nm Technologies and Beyond